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<a href="#nested-classes">Data Structures</a> &#124;
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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_mipi___rx___phy___config.html">XMipi_Rx_Phy_Config</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">The configuration structure for mipi_rx_phy.  <a href="struct_x_mipi___rx___phy___config.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">The Xmipi_rx_phy Controller driver instance data.  <a href="struct_x_mipi___rx___phy.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Macros</h2></td></tr>
<tr class="memitem:ga47f2481f1db47714aff2cff40ae1805a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga47f2481f1db47714aff2cff40ae1805a">XMIPI_RX_PHY_H_</a></td></tr>
<tr class="memdesc:ga47f2481f1db47714aff2cff40ae1805a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="#ga47f2481f1db47714aff2cff40ae1805a">More...</a><br/></td></tr>
<tr class="separator:ga47f2481f1db47714aff2cff40ae1805a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga10de00dc29c09ca2f4cd07b791947303"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga10de00dc29c09ca2f4cd07b791947303">XMIPI_RX_PHY_HW_H_</a></td></tr>
<tr class="memdesc:ga10de00dc29c09ca2f4cd07b791947303"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="#ga10de00dc29c09ca2f4cd07b791947303">More...</a><br/></td></tr>
<tr class="separator:ga10de00dc29c09ca2f4cd07b791947303"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Functions</h2></td></tr>
<tr class="memitem:gadd043232c820116d069c13766ce1d432"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gadd043232c820116d069c13766ce1d432">XMipi_Rx_Phy_CfgInitialize</a> (<a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *InstancePtr, <a class="el" href="struct_x_mipi___rx___phy___config.html">XMipi_Rx_Phy_Config</a> *CfgPtr, UINTPTR EffectiveAddr)</td></tr>
<tr class="memdesc:gadd043232c820116d069c13766ce1d432"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialize the <a class="el" href="struct_x_mipi___rx___phy.html" title="The Xmipi_rx_phy Controller driver instance data. ">XMipi_Rx_Phy</a> instance provided by the caller based on the given Config structure.  <a href="#gadd043232c820116d069c13766ce1d432">More...</a><br/></td></tr>
<tr class="separator:gadd043232c820116d069c13766ce1d432"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga60a0033eef09e3af1f3d38b2642bc990"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga60a0033eef09e3af1f3d38b2642bc990">XMipi_Rx_Phy_Configure</a> (<a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *InstancePtr, u8 Handle, u32 Value)</td></tr>
<tr class="memdesc:ga60a0033eef09e3af1f3d38b2642bc990"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configure the registers of the Mipi_Rx_Phy instance.  <a href="#ga60a0033eef09e3af1f3d38b2642bc990">More...</a><br/></td></tr>
<tr class="separator:ga60a0033eef09e3af1f3d38b2642bc990"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad74a27324b8cc55c67a21a9c2c7a2436"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gad74a27324b8cc55c67a21a9c2c7a2436">XMipi_Rx_Phy_GetRegIntfcPresent</a> (<a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *InstancePtr)</td></tr>
<tr class="memdesc:gad74a27324b8cc55c67a21a9c2c7a2436"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get if register interface is present from the config structure for specified Mipi_Rx_Phy instance.  <a href="#gad74a27324b8cc55c67a21a9c2c7a2436">More...</a><br/></td></tr>
<tr class="separator:gad74a27324b8cc55c67a21a9c2c7a2436"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4149681aae67882912df4493b8e7d66e"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo</a> (<a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *InstancePtr, u8 Handle)</td></tr>
<tr class="memdesc:ga4149681aae67882912df4493b8e7d66e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get information stored in the Mipi_Rx_Phy instance based on the handle passed.  <a href="#ga4149681aae67882912df4493b8e7d66e">More...</a><br/></td></tr>
<tr class="separator:ga4149681aae67882912df4493b8e7d66e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga52f42a2ed7b0acf4df27211b76708ab4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga52f42a2ed7b0acf4df27211b76708ab4">XMipi_Rx_Phy_Reset</a> (<a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga52f42a2ed7b0acf4df27211b76708ab4"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is used to do a soft reset of the Mipi_Rx_Phy IP instance.  <a href="#ga52f42a2ed7b0acf4df27211b76708ab4">More...</a><br/></td></tr>
<tr class="separator:ga52f42a2ed7b0acf4df27211b76708ab4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac84fac31ab197bd3198dd11ca3896435"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gac84fac31ab197bd3198dd11ca3896435">XMipi_Rx_Phy_ClearDataLane</a> (<a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *InstancePtr, u8 DataLane, u32 Mask)</td></tr>
<tr class="memdesc:gac84fac31ab197bd3198dd11ca3896435"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is used to clear the Abort Error (Escape or High Speed) bits in the Data Lane 0 through 3.  <a href="#gac84fac31ab197bd3198dd11ca3896435">More...</a><br/></td></tr>
<tr class="separator:gac84fac31ab197bd3198dd11ca3896435"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafa9a8618d0efffc43b5001c4456dec8c"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gafa9a8618d0efffc43b5001c4456dec8c">XMipi_Rx_Phy_GetClkLaneStatus</a> (<a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *InstancePtr)</td></tr>
<tr class="memdesc:gafa9a8618d0efffc43b5001c4456dec8c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is used to get information about Clock Lane status.  <a href="#gafa9a8618d0efffc43b5001c4456dec8c">More...</a><br/></td></tr>
<tr class="separator:gafa9a8618d0efffc43b5001c4456dec8c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0c21c9093da86aa4159da50ded9b27c5"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga0c21c9093da86aa4159da50ded9b27c5">XMipi_Rx_Phy_GetClkLaneMode</a> (<a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga0c21c9093da86aa4159da50ded9b27c5"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is used to get specific Lane mode information about Clock Lane.  <a href="#ga0c21c9093da86aa4159da50ded9b27c5">More...</a><br/></td></tr>
<tr class="separator:ga0c21c9093da86aa4159da50ded9b27c5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaed445ca4dc94ebbb7ed5b8035a7e914b"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gaed445ca4dc94ebbb7ed5b8035a7e914b">XMipi_Rx_Phy_GetDataLaneStatus</a> (<a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *InstancePtr, u8 DataLane)</td></tr>
<tr class="memdesc:gaed445ca4dc94ebbb7ed5b8035a7e914b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is used to get information about a Data Lane status.  <a href="#gaed445ca4dc94ebbb7ed5b8035a7e914b">More...</a><br/></td></tr>
<tr class="separator:gaed445ca4dc94ebbb7ed5b8035a7e914b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga54671eb4258647bce4fc9cfe2cfa04b1"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga54671eb4258647bce4fc9cfe2cfa04b1">XMipi_Rx_Phy_GetDLCalibStatus</a> (<a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *InstancePtr, u8 DataLane)</td></tr>
<tr class="memdesc:ga54671eb4258647bce4fc9cfe2cfa04b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is used to get Data Lane Calibration status.  <a href="#ga54671eb4258647bce4fc9cfe2cfa04b1">More...</a><br/></td></tr>
<tr class="separator:ga54671eb4258647bce4fc9cfe2cfa04b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaca06750514da41ca96625aeebf2cee64"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gaca06750514da41ca96625aeebf2cee64">XMipi_Rx_Phy_GetDataLaneMode</a> (<a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *InstancePtr, u8 DataLane)</td></tr>
<tr class="memdesc:gaca06750514da41ca96625aeebf2cee64"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is used to get specfic Lane mode information about a Data Lane.  <a href="#gaca06750514da41ca96625aeebf2cee64">More...</a><br/></td></tr>
<tr class="separator:gaca06750514da41ca96625aeebf2cee64"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga451ed3af91fc85637ee4d1ab5de28da3"><td class="memItemLeft" align="right" valign="top">u16&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga451ed3af91fc85637ee4d1ab5de28da3">XMipi_Rx_Phy_GetPacketCount</a> (<a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *InstancePtr, u8 DataLane)</td></tr>
<tr class="memdesc:ga451ed3af91fc85637ee4d1ab5de28da3"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is used to get count of packets received on each lane.  <a href="#ga451ed3af91fc85637ee4d1ab5de28da3">More...</a><br/></td></tr>
<tr class="separator:ga451ed3af91fc85637ee4d1ab5de28da3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafeeea99a20ac3bb4b3c05f64064feb86"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gafeeea99a20ac3bb4b3c05f64064feb86">XMipi_Rx_Phy_GetVersionReg</a> (<a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *InstancePtr)</td></tr>
<tr class="memdesc:gafeeea99a20ac3bb4b3c05f64064feb86"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is used to get Mipi_Rx_Phy Version.  <a href="#gafeeea99a20ac3bb4b3c05f64064feb86">More...</a><br/></td></tr>
<tr class="separator:gafeeea99a20ac3bb4b3c05f64064feb86"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0ac6ef589b022c2aa02bc6e234cc7433"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga0ac6ef589b022c2aa02bc6e234cc7433">XMipi_Rx_Phy_Activate</a> (<a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *InstancePtr, u8 Flag)</td></tr>
<tr class="memdesc:ga0ac6ef589b022c2aa02bc6e234cc7433"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is used to enable or disable the Mipi_Rx_Phy core.  <a href="#ga0ac6ef589b022c2aa02bc6e234cc7433">More...</a><br/></td></tr>
<tr class="separator:ga0ac6ef589b022c2aa02bc6e234cc7433"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5bc7c94c01f1212bbe860efa8982443e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_mipi___rx___phy___config.html">XMipi_Rx_Phy_Config</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga5bc7c94c01f1212bbe860efa8982443e">XMipi_Rx_Phy_LookupConfig</a> (UINTPTR BaseAddress)</td></tr>
<tr class="memdesc:ga5bc7c94c01f1212bbe860efa8982443e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Look up the hardware configuration for a device instance.  <a href="#ga5bc7c94c01f1212bbe860efa8982443e">More...</a><br/></td></tr>
<tr class="separator:ga5bc7c94c01f1212bbe860efa8982443e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga73cfbe4a911c72bccdea37f91d5829d6"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga73cfbe4a911c72bccdea37f91d5829d6">XMipi_Rx_Phy_SelfTest</a> (<a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga73cfbe4a911c72bccdea37f91d5829d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Runs a self-test on the driver/device.  <a href="#ga73cfbe4a911c72bccdea37f91d5829d6">More...</a><br/></td></tr>
<tr class="separator:ga73cfbe4a911c72bccdea37f91d5829d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
mipi_rx_phy Modes</h2></td></tr>
<tr class="memitem:ga0f33ed842e29cb278f24a1c7d661aaa9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga0f33ed842e29cb278f24a1c7d661aaa9">XMIPI_RX_PHY_MODE_MIN</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga0f33ed842e29cb278f24a1c7d661aaa9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lower limit for Mode.  <a href="#ga0f33ed842e29cb278f24a1c7d661aaa9">More...</a><br/></td></tr>
<tr class="separator:ga0f33ed842e29cb278f24a1c7d661aaa9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga12575a833db166780c85a10a45b142c8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga12575a833db166780c85a10a45b142c8">XMIPI_RX_PHY_LOW_POWER_MODE</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga12575a833db166780c85a10a45b142c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lane in Low Power Mode.  <a href="#ga12575a833db166780c85a10a45b142c8">More...</a><br/></td></tr>
<tr class="separator:ga12575a833db166780c85a10a45b142c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga83b17604d921493045f62887dff773ca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga83b17604d921493045f62887dff773ca">XMIPI_RX_PHY_HIGH_POWER_MODE</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:ga83b17604d921493045f62887dff773ca"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lane in High Power Mode.  <a href="#ga83b17604d921493045f62887dff773ca">More...</a><br/></td></tr>
<tr class="separator:ga83b17604d921493045f62887dff773ca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6ff6bab049c8e69e8ccbebc8b43b6eb7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga6ff6bab049c8e69e8ccbebc8b43b6eb7">XMIPI_RX_PHY_ESCAPE_MODE</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:ga6ff6bab049c8e69e8ccbebc8b43b6eb7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lane in Escape Mode.  <a href="#ga6ff6bab049c8e69e8ccbebc8b43b6eb7">More...</a><br/></td></tr>
<tr class="separator:ga6ff6bab049c8e69e8ccbebc8b43b6eb7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga34e4e2c11b6b212760e6e372cccde8e1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga34e4e2c11b6b212760e6e372cccde8e1">XMIPI_RX_PHY_MODE_MAX</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:ga34e4e2c11b6b212760e6e372cccde8e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Upper Limit for mode.  <a href="#ga34e4e2c11b6b212760e6e372cccde8e1">More...</a><br/></td></tr>
<tr class="separator:ga34e4e2c11b6b212760e6e372cccde8e1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga91cf5eb7c138a6a6f2bc4f05be160ea8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga91cf5eb7c138a6a6f2bc4f05be160ea8">XMIPI_RX_PHY_MAX_LANES_V10</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:ga91cf5eb7c138a6a6f2bc4f05be160ea8"><td class="mdescLeft">&#160;</td><td class="mdescRight">V1.0 supports 4 Lanes.  <a href="#ga91cf5eb7c138a6a6f2bc4f05be160ea8">More...</a><br/></td></tr>
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mipi_rx_phy Info Handles</h2></td></tr>
<tr class="memitem:ga0039d3d6608c07dff89ab4b92d2e4159"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga0039d3d6608c07dff89ab4b92d2e4159">XMIPI_RX_PHY_HANDLE_MIN</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga0039d3d6608c07dff89ab4b92d2e4159"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lower Bound for XMIPI_RX_PHY_HANDLE.  <a href="#ga0039d3d6608c07dff89ab4b92d2e4159">More...</a><br/></td></tr>
<tr class="separator:ga0039d3d6608c07dff89ab4b92d2e4159"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0972f732a6337d400b421b31a923bd89"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga0972f732a6337d400b421b31a923bd89">XMIPI_RX_PHY_HANDLE_IDELAY</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga0972f732a6337d400b421b31a923bd89"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handle for IDELAY Reg.  <a href="#ga0972f732a6337d400b421b31a923bd89">More...</a><br/></td></tr>
<tr class="separator:ga0972f732a6337d400b421b31a923bd89"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad4a4803f13f2ae21cfc4443b4f74ceb3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gad4a4803f13f2ae21cfc4443b4f74ceb3">XMIPI_RX_PHY_HANDLE_INIT_TIMER</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:gad4a4803f13f2ae21cfc4443b4f74ceb3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handle for Initialization Timer.  <a href="#gad4a4803f13f2ae21cfc4443b4f74ceb3">More...</a><br/></td></tr>
<tr class="separator:gad4a4803f13f2ae21cfc4443b4f74ceb3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa08e333d5f15043cd3487c45ce478248"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gaa08e333d5f15043cd3487c45ce478248">XMIPI_RX_PHY_HANDLE_WAKEUP</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:gaa08e333d5f15043cd3487c45ce478248"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handle for Wakeup timer.  <a href="#gaa08e333d5f15043cd3487c45ce478248">More...</a><br/></td></tr>
<tr class="separator:gaa08e333d5f15043cd3487c45ce478248"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga72222b2af839769c09e80f143f2da026"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga72222b2af839769c09e80f143f2da026">XMIPI_RX_PHY_HANDLE_HSTIMEOUT</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:ga72222b2af839769c09e80f143f2da026"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handle for HS Timeout.  <a href="#ga72222b2af839769c09e80f143f2da026">More...</a><br/></td></tr>
<tr class="separator:ga72222b2af839769c09e80f143f2da026"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac915d728a8c6106c1deef751bdb2f93e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gac915d728a8c6106c1deef751bdb2f93e">XMIPI_RX_PHY_HANDLE_ESCTIMEOUT</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:gac915d728a8c6106c1deef751bdb2f93e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handle for Escape Timeout.  <a href="#gac915d728a8c6106c1deef751bdb2f93e">More...</a><br/></td></tr>
<tr class="separator:gac915d728a8c6106c1deef751bdb2f93e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa79e40f54ad9778f3995f8ccfcb09fd8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gaa79e40f54ad9778f3995f8ccfcb09fd8">XMIPI_RX_PHY_HANDLE_CLKLANE</a>&#160;&#160;&#160;5</td></tr>
<tr class="memdesc:gaa79e40f54ad9778f3995f8ccfcb09fd8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handle for Clock Lane.  <a href="#gaa79e40f54ad9778f3995f8ccfcb09fd8">More...</a><br/></td></tr>
<tr class="separator:gaa79e40f54ad9778f3995f8ccfcb09fd8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafde9bac4868ce2d47e85c0de32532298"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gafde9bac4868ce2d47e85c0de32532298">XMIPI_RX_PHY_HANDLE_DLANE0</a>&#160;&#160;&#160;6</td></tr>
<tr class="memdesc:gafde9bac4868ce2d47e85c0de32532298"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handle for Data Lane 0.  <a href="#gafde9bac4868ce2d47e85c0de32532298">More...</a><br/></td></tr>
<tr class="separator:gafde9bac4868ce2d47e85c0de32532298"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf50cbba445009363e9a2821642d28984"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gaf50cbba445009363e9a2821642d28984">XMIPI_RX_PHY_HANDLE_DLANE1</a>&#160;&#160;&#160;7</td></tr>
<tr class="memdesc:gaf50cbba445009363e9a2821642d28984"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handle for Data Lane 1.  <a href="#gaf50cbba445009363e9a2821642d28984">More...</a><br/></td></tr>
<tr class="separator:gaf50cbba445009363e9a2821642d28984"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad3558fcc5200ad583a504c61ce1f0d15"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gad3558fcc5200ad583a504c61ce1f0d15">XMIPI_RX_PHY_HANDLE_DLANE2</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:gad3558fcc5200ad583a504c61ce1f0d15"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handle for Data Lane 2.  <a href="#gad3558fcc5200ad583a504c61ce1f0d15">More...</a><br/></td></tr>
<tr class="separator:gad3558fcc5200ad583a504c61ce1f0d15"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaffb241b59b61b4dabff3a17173f34d5e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gaffb241b59b61b4dabff3a17173f34d5e">XMIPI_RX_PHY_HANDLE_DLANE3</a>&#160;&#160;&#160;9</td></tr>
<tr class="memdesc:gaffb241b59b61b4dabff3a17173f34d5e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handle for Data Lane 3.  <a href="#gaffb241b59b61b4dabff3a17173f34d5e">More...</a><br/></td></tr>
<tr class="separator:gaffb241b59b61b4dabff3a17173f34d5e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9ecbd14c9768eeff2b17f537d338f775"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga9ecbd14c9768eeff2b17f537d338f775">XMIPI_RX_PHY_HANDLE_HSSETTLE0</a>&#160;&#160;&#160;10</td></tr>
<tr class="memdesc:ga9ecbd14c9768eeff2b17f537d338f775"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handle for HS SETTLE L0.  <a href="#ga9ecbd14c9768eeff2b17f537d338f775">More...</a><br/></td></tr>
<tr class="separator:ga9ecbd14c9768eeff2b17f537d338f775"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga078f5a607947c32b21570f1640ea1a4a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga078f5a607947c32b21570f1640ea1a4a">XMIPI_RX_PHY_HANDLE_HSSETTLE1</a>&#160;&#160;&#160;11</td></tr>
<tr class="memdesc:ga078f5a607947c32b21570f1640ea1a4a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handle for HS SETTLE L1.  <a href="#ga078f5a607947c32b21570f1640ea1a4a">More...</a><br/></td></tr>
<tr class="separator:ga078f5a607947c32b21570f1640ea1a4a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga568c5e242ff59d6b4f222f1642149406"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga568c5e242ff59d6b4f222f1642149406">XMIPI_RX_PHY_HANDLE_HSSETTLE2</a>&#160;&#160;&#160;12</td></tr>
<tr class="memdesc:ga568c5e242ff59d6b4f222f1642149406"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handle for HS SETTLE L2.  <a href="#ga568c5e242ff59d6b4f222f1642149406">More...</a><br/></td></tr>
<tr class="separator:ga568c5e242ff59d6b4f222f1642149406"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga473e22be644740e67566ce0ce2940124"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga473e22be644740e67566ce0ce2940124">XMIPI_RX_PHY_HANDLE_HSSETTLE3</a>&#160;&#160;&#160;13</td></tr>
<tr class="memdesc:ga473e22be644740e67566ce0ce2940124"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handle for HS SETTLE L3.  <a href="#ga473e22be644740e67566ce0ce2940124">More...</a><br/></td></tr>
<tr class="separator:ga473e22be644740e67566ce0ce2940124"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabb969dbe56ae53bb6fec1916917be1b5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gabb969dbe56ae53bb6fec1916917be1b5">XMIPI_RX_PHY_HANDLE_MAX</a>&#160;&#160;&#160;14</td></tr>
<tr class="memdesc:gabb969dbe56ae53bb6fec1916917be1b5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Upper Bound for XMIPI_RX_PHY_HANDLE.  <a href="#gabb969dbe56ae53bb6fec1916917be1b5">More...</a><br/></td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
mipi_rx_phy HSTIMEOUT range</h2></td></tr>
<tr class="memitem:ga368643a84916a08df985dd961cf42d52"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga368643a84916a08df985dd961cf42d52"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XMIPI_RX_PHY_HS_TIMEOUT_MIN_VALUE</b>&#160;&#160;&#160;10000UL</td></tr>
<tr class="separator:ga368643a84916a08df985dd961cf42d52"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1d7f56650d0da43285295644eb951100"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1d7f56650d0da43285295644eb951100"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XMIPI_RX_PHY_HS_TIMEOUT_MAX_VALUE</b>&#160;&#160;&#160;65541UL</td></tr>
<tr class="separator:ga1d7f56650d0da43285295644eb951100"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
mipi_rx_phy HSSETTLE range</h2></td></tr>
<tr class="memitem:ga379ac70918b08991b5629895cdbdca0f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga379ac70918b08991b5629895cdbdca0f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XMIPI_RX_PHY_HS_SETTLE_MAX_VALUE</b>&#160;&#160;&#160;0x1FF</td></tr>
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mipi_rx_phy Flags to Enable or Disable core</h2></td></tr>
<tr class="memitem:ga52cb6c5b38df470a0f7e71c41d7e059e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga52cb6c5b38df470a0f7e71c41d7e059e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XMIPI_RX_PHY_ENABLE_FLAG</b>&#160;&#160;&#160;1</td></tr>
<tr class="separator:ga52cb6c5b38df470a0f7e71c41d7e059e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf4e1dd0a01fee5503124e2bd532f02ce"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf4e1dd0a01fee5503124e2bd532f02ce"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XMIPI_RX_PHY_DISABLE_FLAG</b>&#160;&#160;&#160;0</td></tr>
<tr class="separator:gaf4e1dd0a01fee5503124e2bd532f02ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
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Device registers</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpe905567f3f1e4630e21d2f8192509576"></a>Register sets of MIPI_RX_PHY </p>
</td></tr>
<tr class="memitem:ga0bf404750dfcaaefdd04d672d4a34ed2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga0bf404750dfcaaefdd04d672d4a34ed2">XMIPI_RX_PHY_CTRL_REG_OFFSET</a>&#160;&#160;&#160;0x00000000</td></tr>
<tr class="memdesc:ga0bf404750dfcaaefdd04d672d4a34ed2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control Register.  <a href="#ga0bf404750dfcaaefdd04d672d4a34ed2">More...</a><br/></td></tr>
<tr class="separator:ga0bf404750dfcaaefdd04d672d4a34ed2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf427e80f588294f6bd021db121fc76fd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gaf427e80f588294f6bd021db121fc76fd">XMIPI_RX_PHY_VERSION_REG_OFFSET</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gaf427e80f588294f6bd021db121fc76fd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core Version Register.  <a href="#gaf427e80f588294f6bd021db121fc76fd">More...</a><br/></td></tr>
<tr class="separator:gaf427e80f588294f6bd021db121fc76fd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5d73b98adf4b04216bb1742cc3ad92d6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga5d73b98adf4b04216bb1742cc3ad92d6">XMIPI_RX_PHY_INIT_TIMER_REG_OFFSET</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga5d73b98adf4b04216bb1742cc3ad92d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialization Timer Register.  <a href="#ga5d73b98adf4b04216bb1742cc3ad92d6">More...</a><br/></td></tr>
<tr class="separator:ga5d73b98adf4b04216bb1742cc3ad92d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gace1a808a2597c0a1395016ec4de67d8a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gace1a808a2597c0a1395016ec4de67d8a">XMIPI_RX_PHY_HSTIMEOUT_REG_OFFSET</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:gace1a808a2597c0a1395016ec4de67d8a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Watchdog timeout in HS mode Register.  <a href="#gace1a808a2597c0a1395016ec4de67d8a">More...</a><br/></td></tr>
<tr class="separator:gace1a808a2597c0a1395016ec4de67d8a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1f2a7ab905af5a63575745e79fa1afef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga1f2a7ab905af5a63575745e79fa1afef">XMIPI_RX_PHY_ESCTIMEOUT_REG_OFFSET</a>&#160;&#160;&#160;0x00000014</td></tr>
<tr class="memdesc:ga1f2a7ab905af5a63575745e79fa1afef"><td class="mdescLeft">&#160;</td><td class="mdescRight">Goto Stop state on timeout timer Register.  <a href="#ga1f2a7ab905af5a63575745e79fa1afef">More...</a><br/></td></tr>
<tr class="separator:ga1f2a7ab905af5a63575745e79fa1afef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6df3cddb2f8c6136193423656e1f8e54"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga6df3cddb2f8c6136193423656e1f8e54">XMIPI_RX_PHY_CLSTATUS_REG_OFFSET</a>&#160;&#160;&#160;0x00000018</td></tr>
<tr class="memdesc:ga6df3cddb2f8c6136193423656e1f8e54"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clk lane PHY error Status Register.  <a href="#ga6df3cddb2f8c6136193423656e1f8e54">More...</a><br/></td></tr>
<tr class="separator:ga6df3cddb2f8c6136193423656e1f8e54"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7ca8cc7e96c85d80a747864154b5ffa0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga7ca8cc7e96c85d80a747864154b5ffa0">XMIPI_RX_PHY_DL0STATUS_REG_OFFSET</a>&#160;&#160;&#160;0x0000001C</td></tr>
<tr class="memdesc:ga7ca8cc7e96c85d80a747864154b5ffa0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data lane 0 PHY error Status Register.  <a href="#ga7ca8cc7e96c85d80a747864154b5ffa0">More...</a><br/></td></tr>
<tr class="separator:ga7ca8cc7e96c85d80a747864154b5ffa0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4d6de41a345ab9b0da5a07936f3a5d8a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga4d6de41a345ab9b0da5a07936f3a5d8a">XMIPI_RX_PHY_DL1STATUS_REG_OFFSET</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga4d6de41a345ab9b0da5a07936f3a5d8a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data lane 1 PHY error Status Register.  <a href="#ga4d6de41a345ab9b0da5a07936f3a5d8a">More...</a><br/></td></tr>
<tr class="separator:ga4d6de41a345ab9b0da5a07936f3a5d8a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa7867d266b24387c2a89bb4c8e61306b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gaa7867d266b24387c2a89bb4c8e61306b">XMIPI_RX_PHY_DL2STATUS_REG_OFFSET</a>&#160;&#160;&#160;0x00000024</td></tr>
<tr class="memdesc:gaa7867d266b24387c2a89bb4c8e61306b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data lane 2 PHY error Status Register.  <a href="#gaa7867d266b24387c2a89bb4c8e61306b">More...</a><br/></td></tr>
<tr class="separator:gaa7867d266b24387c2a89bb4c8e61306b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae602e9d94b72de6818a5b3f9e5b2bc82"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gae602e9d94b72de6818a5b3f9e5b2bc82">XMIPI_RX_PHY_DL3STATUS_REG_OFFSET</a>&#160;&#160;&#160;0x00000028</td></tr>
<tr class="memdesc:gae602e9d94b72de6818a5b3f9e5b2bc82"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data lane 3 PHY error Status Register.  <a href="#gae602e9d94b72de6818a5b3f9e5b2bc82">More...</a><br/></td></tr>
<tr class="separator:gae602e9d94b72de6818a5b3f9e5b2bc82"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga941337f26bc908ba365194c7d1e152ab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga941337f26bc908ba365194c7d1e152ab">XMIPI_RX_PHY_HSSETTLE0_REG_OFFSET</a>&#160;&#160;&#160;0x00000030</td></tr>
<tr class="memdesc:ga941337f26bc908ba365194c7d1e152ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">HS Settle Register L0.  <a href="#ga941337f26bc908ba365194c7d1e152ab">More...</a><br/></td></tr>
<tr class="separator:ga941337f26bc908ba365194c7d1e152ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga811dbc44fe9d3b4dc258652de27d661c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga811dbc44fe9d3b4dc258652de27d661c">XMIPI_RX_PHY_HSSETTLE1_REG_OFFSET</a>&#160;&#160;&#160;0x00000048</td></tr>
<tr class="memdesc:ga811dbc44fe9d3b4dc258652de27d661c"><td class="mdescLeft">&#160;</td><td class="mdescRight">HS Settle Register L1.  <a href="#ga811dbc44fe9d3b4dc258652de27d661c">More...</a><br/></td></tr>
<tr class="separator:ga811dbc44fe9d3b4dc258652de27d661c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6c837a9e2b95486169ad376478bfc14e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga6c837a9e2b95486169ad376478bfc14e">XMIPI_RX_PHY_HSSETTLE2_REG_OFFSET</a>&#160;&#160;&#160;0x0000004C</td></tr>
<tr class="memdesc:ga6c837a9e2b95486169ad376478bfc14e"><td class="mdescLeft">&#160;</td><td class="mdescRight">HS Settle Register L2.  <a href="#ga6c837a9e2b95486169ad376478bfc14e">More...</a><br/></td></tr>
<tr class="separator:ga6c837a9e2b95486169ad376478bfc14e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga832f2a3a308197b899ba0f7d0b33e908"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga832f2a3a308197b899ba0f7d0b33e908">XMIPI_RX_PHY_HSSETTLE3_REG_OFFSET</a>&#160;&#160;&#160;0x00000050</td></tr>
<tr class="memdesc:ga832f2a3a308197b899ba0f7d0b33e908"><td class="mdescLeft">&#160;</td><td class="mdescRight">HS Settle Register L3.  <a href="#ga832f2a3a308197b899ba0f7d0b33e908">More...</a><br/></td></tr>
<tr class="separator:ga832f2a3a308197b899ba0f7d0b33e908"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Bitmasks and offsets of XMIPI_RX_PHY_CTRL_REG_OFFSET register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpcb76cd530f4f5f2eaaf9141a54a5a2d0"></a>This register is used for the enabling/disabling and resetting the MIPI_RX_PHY </p>
</td></tr>
<tr class="memitem:ga99a08282c67427601f56d2ad64234ed6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga99a08282c67427601f56d2ad64234ed6">XMIPI_RX_PHY_CTRL_REG_SOFTRESET_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga99a08282c67427601f56d2ad64234ed6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Soft Reset.  <a href="#ga99a08282c67427601f56d2ad64234ed6">More...</a><br/></td></tr>
<tr class="separator:ga99a08282c67427601f56d2ad64234ed6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaec198293afc07be517b0ae8f92837d2c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gaec198293afc07be517b0ae8f92837d2c">XMIPI_RX_PHY_CTRL_REG_PHYEN_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gaec198293afc07be517b0ae8f92837d2c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable/Disable controller.  <a href="#gaec198293afc07be517b0ae8f92837d2c">More...</a><br/></td></tr>
<tr class="separator:gaec198293afc07be517b0ae8f92837d2c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad2a85cb1a79f05bcfe068d2a5bb03233"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gad2a85cb1a79f05bcfe068d2a5bb03233">XMIPI_RX_PHY_CTRL_REG_SOFTRESET_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:gad2a85cb1a79f05bcfe068d2a5bb03233"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Soft Reset.  <a href="#gad2a85cb1a79f05bcfe068d2a5bb03233">More...</a><br/></td></tr>
<tr class="separator:gad2a85cb1a79f05bcfe068d2a5bb03233"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaceeabb8c562fc7a8eedf90bbdd63b4c5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gaceeabb8c562fc7a8eedf90bbdd63b4c5">XMIPI_RX_PHY_CTRL_REG_PHYEN_OFFSET</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:gaceeabb8c562fc7a8eedf90bbdd63b4c5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for PHY Enable.  <a href="#gaceeabb8c562fc7a8eedf90bbdd63b4c5">More...</a><br/></td></tr>
<tr class="separator:gaceeabb8c562fc7a8eedf90bbdd63b4c5"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Bitmasks and offsets of XMIPI_RX_PHY_INIT_REG_OFFSET register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpdd7614e620854ae78b0c8f0b3f85838a"></a>This register is used for lane Initialization.</p>
<p>Recommended to use 1ms or longer in for TX mode and 200us-500us for RX mode </p>
</td></tr>
<tr class="memitem:gab750cb7ee4477ebf02dee74a7e912949"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gab750cb7ee4477ebf02dee74a7e912949">XMIPI_RX_PHY_INIT_REG_VAL_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:gab750cb7ee4477ebf02dee74a7e912949"><td class="mdescLeft">&#160;</td><td class="mdescRight">Init Timer value in ns.  <a href="#gab750cb7ee4477ebf02dee74a7e912949">More...</a><br/></td></tr>
<tr class="separator:gab750cb7ee4477ebf02dee74a7e912949"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga02c8e40953545ada2100d4431ffe3061"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga02c8e40953545ada2100d4431ffe3061">XMIPI_RX_PHY_INIT_REG_VAL_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga02c8e40953545ada2100d4431ffe3061"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Init Timer.  <a href="#ga02c8e40953545ada2100d4431ffe3061">More...</a><br/></td></tr>
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Bitmask and offset of XMIPI_RX_PHY_HSTIMEOUT_REG_OFFSET register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp70e78ae9b047885af5fed9166d160c78"></a>This register is used to program watchdog timer in high speed mode.</p>
<p>Default value is 65541. Valid range 1000-65541. </p>
</td></tr>
<tr class="memitem:ga2b315903c952abd8e09c802a1a6be4c3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga2b315903c952abd8e09c802a1a6be4c3">XMIPI_RX_PHY_HSTIMEOUT_REG_TIMEOUT_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:ga2b315903c952abd8e09c802a1a6be4c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">HS_RX_TIMEOUT Received.  <a href="#ga2b315903c952abd8e09c802a1a6be4c3">More...</a><br/></td></tr>
<tr class="separator:ga2b315903c952abd8e09c802a1a6be4c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadec1619af7a2de87d591812729bc52d1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gadec1619af7a2de87d591812729bc52d1">XMIPI_RX_PHY_HSTIMEOUT_REG_TIMEOUT_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:gadec1619af7a2de87d591812729bc52d1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Timeout.  <a href="#gadec1619af7a2de87d591812729bc52d1">More...</a><br/></td></tr>
<tr class="separator:gadec1619af7a2de87d591812729bc52d1"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Bitmask and offset of XMIPI_RX_PHY_ESCTIMEOUT_REG_OFFSET register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp5c968db87a2ac03474fc17a4068cfff8"></a>This register contains Rx Data Lanes timeout for watchdog timer in escape mode. </p>
</td></tr>
<tr class="memitem:ga57f8374c40686716eb09f598db90d2d7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga57f8374c40686716eb09f598db90d2d7">XMIPI_RX_PHY_ESCTIMEOUT_REG_VAL_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:ga57f8374c40686716eb09f598db90d2d7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Escape Timout Value.  <a href="#ga57f8374c40686716eb09f598db90d2d7">More...</a><br/></td></tr>
<tr class="separator:ga57f8374c40686716eb09f598db90d2d7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga79f52cbaa7e2faa9b99f6c7f1c901d41"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga79f52cbaa7e2faa9b99f6c7f1c901d41">XMIPI_RX_PHY_ESCTIMEOUT_REG_VAL_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga79f52cbaa7e2faa9b99f6c7f1c901d41"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Escape Timeout.  <a href="#ga79f52cbaa7e2faa9b99f6c7f1c901d41">More...</a><br/></td></tr>
<tr class="separator:ga79f52cbaa7e2faa9b99f6c7f1c901d41"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Bitmask and offset of XMIPI_RX_PHY_CLSTATUS_REG_OFFSET register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpa31933f6f5fb9da69976126276c95e99"></a>This register contains the clock lane status and state machine control. </p>
</td></tr>
<tr class="memitem:ga39c1f0241f05d6c2dd4e6d86a952f1f4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga39c1f0241f05d6c2dd4e6d86a952f1f4">XMIPI_RX_PHY_CLSTATUS_REG_ERRCTRL_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga39c1f0241f05d6c2dd4e6d86a952f1f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock lane control error.  <a href="#ga39c1f0241f05d6c2dd4e6d86a952f1f4">More...</a><br/></td></tr>
<tr class="separator:ga39c1f0241f05d6c2dd4e6d86a952f1f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8db6d7f19e0431ee20321b3a635a2eca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga8db6d7f19e0431ee20321b3a635a2eca">XMIPI_RX_PHY_CLSTATUS_REG_STOPSTATE_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga8db6d7f19e0431ee20321b3a635a2eca"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock lane stop state.  <a href="#ga8db6d7f19e0431ee20321b3a635a2eca">More...</a><br/></td></tr>
<tr class="separator:ga8db6d7f19e0431ee20321b3a635a2eca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1004d17945d6005324cc685f1d7038ba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga1004d17945d6005324cc685f1d7038ba">XMIPI_RX_PHY_CLSTATUS_REG_INITDONE_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga1004d17945d6005324cc685f1d7038ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialization done bit.  <a href="#ga1004d17945d6005324cc685f1d7038ba">More...</a><br/></td></tr>
<tr class="separator:ga1004d17945d6005324cc685f1d7038ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac8c1a0b393d70ec50205cdff482db809"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gac8c1a0b393d70ec50205cdff482db809">XMIPI_RX_PHY_CLSTATUS_REG_ULPS_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gac8c1a0b393d70ec50205cdff482db809"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set in ULPS mode.  <a href="#gac8c1a0b393d70ec50205cdff482db809">More...</a><br/></td></tr>
<tr class="separator:gac8c1a0b393d70ec50205cdff482db809"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0b072dcfbf16b94c76a98a422d609a8f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga0b072dcfbf16b94c76a98a422d609a8f">XMIPI_RX_PHY_CLSTATUS_REG_MODE_MASK</a>&#160;&#160;&#160;0x00000003</td></tr>
<tr class="memdesc:ga0b072dcfbf16b94c76a98a422d609a8f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Low, High, Esc mode.  <a href="#ga0b072dcfbf16b94c76a98a422d609a8f">More...</a><br/></td></tr>
<tr class="separator:ga0b072dcfbf16b94c76a98a422d609a8f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga711f31fdbd2533e3ecaa03ec794cf127"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga711f31fdbd2533e3ecaa03ec794cf127"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XMIPI_RX_PHY_CLSTATUS_ALLMASK</b></td></tr>
<tr class="separator:ga711f31fdbd2533e3ecaa03ec794cf127"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadbad3f46c30270a90ef31180b87631b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gadbad3f46c30270a90ef31180b87631b8">XMIPI_RX_PHY_CLSTATUS_REG_ERRCTRL_OFFSET</a>&#160;&#160;&#160;5</td></tr>
<tr class="memdesc:gadbad3f46c30270a90ef31180b87631b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Control Error on Clock.  <a href="#gadbad3f46c30270a90ef31180b87631b8">More...</a><br/></td></tr>
<tr class="separator:gadbad3f46c30270a90ef31180b87631b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6590b147d777602a6a0196968c3c65bd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga6590b147d777602a6a0196968c3c65bd">XMIPI_RX_PHY_CLSTATUS_REG_STOPSTATE_OFFSET</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:ga6590b147d777602a6a0196968c3c65bd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Stop State on Clock.  <a href="#ga6590b147d777602a6a0196968c3c65bd">More...</a><br/></td></tr>
<tr class="separator:ga6590b147d777602a6a0196968c3c65bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8d24544680c66148c097358ce8b33727"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga8d24544680c66148c097358ce8b33727">XMIPI_RX_PHY_CLSTATUS_REG_INITDONE_OFFSET</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:ga8d24544680c66148c097358ce8b33727"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Initialization Done.  <a href="#ga8d24544680c66148c097358ce8b33727">More...</a><br/></td></tr>
<tr class="separator:ga8d24544680c66148c097358ce8b33727"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga276f3c942ce84cd5cce3340f986845ee"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga276f3c942ce84cd5cce3340f986845ee">XMIPI_RX_PHY_CLSTATUS_REG_ULPS_OFFSET</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:ga276f3c942ce84cd5cce3340f986845ee"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for ULPS.  <a href="#ga276f3c942ce84cd5cce3340f986845ee">More...</a><br/></td></tr>
<tr class="separator:ga276f3c942ce84cd5cce3340f986845ee"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0e493b03e48ae8ded1acc92f89d19b83"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga0e493b03e48ae8ded1acc92f89d19b83">XMIPI_RX_PHY_CLSTATUS_REG_MODE_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga0e493b03e48ae8ded1acc92f89d19b83"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Mode bits.  <a href="#ga0e493b03e48ae8ded1acc92f89d19b83">More...</a><br/></td></tr>
<tr class="separator:ga0e493b03e48ae8ded1acc92f89d19b83"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Bitmasks and offsets of XMIPI_RX_PHY_DLxSTATUS_REG_OFFSET register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpe934d7acd265cd3be79cdd30406f1702"></a>This register contains the data lanes status </p>
</td></tr>
<tr class="memitem:ga57c759b34a6fc44b9b6bc969d84b949f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga57c759b34a6fc44b9b6bc969d84b949f">XMIPI_RX_PHY_DLXSTATUS_REG_PACKETCOUNT_MASK</a>&#160;&#160;&#160;0xFFFF0000</td></tr>
<tr class="memdesc:ga57c759b34a6fc44b9b6bc969d84b949f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Packet Count.  <a href="#ga57c759b34a6fc44b9b6bc969d84b949f">More...</a><br/></td></tr>
<tr class="separator:ga57c759b34a6fc44b9b6bc969d84b949f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae96674943b4c7ac2ef7f24e16d114f5e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gae96674943b4c7ac2ef7f24e16d114f5e">XMIPI_RX_PHY_DLXSTATUS_REG_CALIB_STATUS_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:gae96674943b4c7ac2ef7f24e16d114f5e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Calib status.  <a href="#gae96674943b4c7ac2ef7f24e16d114f5e">More...</a><br/></td></tr>
<tr class="separator:gae96674943b4c7ac2ef7f24e16d114f5e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae734cd3c1776660119a146b701d23039"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gae734cd3c1776660119a146b701d23039">XMIPI_RX_PHY_DLXSTATUS_REG_CALIB_COMPLETE_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:gae734cd3c1776660119a146b701d23039"><td class="mdescLeft">&#160;</td><td class="mdescRight">Calib complete.  <a href="#gae734cd3c1776660119a146b701d23039">More...</a><br/></td></tr>
<tr class="separator:gae734cd3c1776660119a146b701d23039"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9398f883326211edd06dc8d2c7bb1017"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga9398f883326211edd06dc8d2c7bb1017">XMIPI_RX_PHY_DLXSTATUS_REG_STOP_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga9398f883326211edd06dc8d2c7bb1017"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stop State on data lane.  <a href="#ga9398f883326211edd06dc8d2c7bb1017">More...</a><br/></td></tr>
<tr class="separator:ga9398f883326211edd06dc8d2c7bb1017"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga193d957c5131a06eb4edf387464e8b23"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga193d957c5131a06eb4edf387464e8b23">XMIPI_RX_PHY_DLXSTATUS_REG_ESCABRT_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga193d957c5131a06eb4edf387464e8b23"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set on Data Lane Esc timeout occurs.  <a href="#ga193d957c5131a06eb4edf387464e8b23">More...</a><br/></td></tr>
<tr class="separator:ga193d957c5131a06eb4edf387464e8b23"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga80f071df87fac8194c77e2b17ca96f89"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga80f071df87fac8194c77e2b17ca96f89">XMIPI_RX_PHY_DLXSTATUS_REG_HSABRT_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga80f071df87fac8194c77e2b17ca96f89"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set on Data Lane HS timeout.  <a href="#ga80f071df87fac8194c77e2b17ca96f89">More...</a><br/></td></tr>
<tr class="separator:ga80f071df87fac8194c77e2b17ca96f89"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga375d4e779b8a019e67f724697281698f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga375d4e779b8a019e67f724697281698f">XMIPI_RX_PHY_DLXSTATUS_REG_INITDONE_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga375d4e779b8a019e67f724697281698f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set after initialization.  <a href="#ga375d4e779b8a019e67f724697281698f">More...</a><br/></td></tr>
<tr class="separator:ga375d4e779b8a019e67f724697281698f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga17bd1c2c7ce0df5dbd19c46e6ea3feb4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga17bd1c2c7ce0df5dbd19c46e6ea3feb4">XMIPI_RX_PHY_DLXSTATUS_REG_ULPS_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga17bd1c2c7ce0df5dbd19c46e6ea3feb4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set when MIPI_RX_PHY in ULPS mode.  <a href="#ga17bd1c2c7ce0df5dbd19c46e6ea3feb4">More...</a><br/></td></tr>
<tr class="separator:ga17bd1c2c7ce0df5dbd19c46e6ea3feb4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8b20becb98cc3e299a6791e4a27165e5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga8b20becb98cc3e299a6791e4a27165e5">XMIPI_RX_PHY_DLXSTATUS_REG_MODE_MASK</a>&#160;&#160;&#160;0x00000003</td></tr>
<tr class="memdesc:ga8b20becb98cc3e299a6791e4a27165e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control Mode (Esc, Low, High) of Data Lane.  <a href="#ga8b20becb98cc3e299a6791e4a27165e5">More...</a><br/></td></tr>
<tr class="separator:ga8b20becb98cc3e299a6791e4a27165e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2cbc32ec0c5d7ba9dda469abcac52d47"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2cbc32ec0c5d7ba9dda469abcac52d47"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XMIPI_RX_PHY_DLXSTATUS_ALLMASK</b></td></tr>
<tr class="separator:ga2cbc32ec0c5d7ba9dda469abcac52d47"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga998420b025e47070ad9a0d79ff4068b5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga998420b025e47070ad9a0d79ff4068b5">XMIPI_RX_PHY_DLXSTATUS_REG_PACKCOUNT_OFFSET</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga998420b025e47070ad9a0d79ff4068b5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset packet count.  <a href="#ga998420b025e47070ad9a0d79ff4068b5">More...</a><br/></td></tr>
<tr class="separator:ga998420b025e47070ad9a0d79ff4068b5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8ab0be5e794c5b009c0fe65359589ac5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga8ab0be5e794c5b009c0fe65359589ac5">XMIPI_RX_PHY_DLXSTATUS_REG_CALIB_STATUS_OFFSET</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:ga8ab0be5e794c5b009c0fe65359589ac5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset calib status.  <a href="#ga8ab0be5e794c5b009c0fe65359589ac5">More...</a><br/></td></tr>
<tr class="separator:ga8ab0be5e794c5b009c0fe65359589ac5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4096f64ca0e39e289b86235fca5a037c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga4096f64ca0e39e289b86235fca5a037c">XMIPI_RX_PHY_DLXSTATUS_REG_CALIB_COMPLETE_OFFSET</a>&#160;&#160;&#160;7</td></tr>
<tr class="memdesc:ga4096f64ca0e39e289b86235fca5a037c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset Calib complete.  <a href="#ga4096f64ca0e39e289b86235fca5a037c">More...</a><br/></td></tr>
<tr class="separator:ga4096f64ca0e39e289b86235fca5a037c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8014b37b88e35bbf981445e019063b64"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga8014b37b88e35bbf981445e019063b64">XMIPI_RX_PHY_DLXSTATUS_REG_STOP_OFFSET</a>&#160;&#160;&#160;6</td></tr>
<tr class="memdesc:ga8014b37b88e35bbf981445e019063b64"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Stop State.  <a href="#ga8014b37b88e35bbf981445e019063b64">More...</a><br/></td></tr>
<tr class="separator:ga8014b37b88e35bbf981445e019063b64"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7e3da7655adcb229ff3b0405df9fda81"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga7e3da7655adcb229ff3b0405df9fda81">XMIPI_RX_PHY_DLXSTATUS_REG_ESCABRT_OFFSET</a>&#160;&#160;&#160;5</td></tr>
<tr class="memdesc:ga7e3da7655adcb229ff3b0405df9fda81"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Escape Abort.  <a href="#ga7e3da7655adcb229ff3b0405df9fda81">More...</a><br/></td></tr>
<tr class="separator:ga7e3da7655adcb229ff3b0405df9fda81"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga848eac0c720848135936180fe5565fcf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga848eac0c720848135936180fe5565fcf">XMIPI_RX_PHY_DLXSTATUS_REG_HSABRT_OFFSET</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:ga848eac0c720848135936180fe5565fcf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for High Speed Abort.  <a href="#ga848eac0c720848135936180fe5565fcf">More...</a><br/></td></tr>
<tr class="separator:ga848eac0c720848135936180fe5565fcf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac7e2936c9950b54b267e8a974681012d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gac7e2936c9950b54b267e8a974681012d">XMIPI_RX_PHY_DLXSTATUS_REG_INITDONE_OFFSET</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:gac7e2936c9950b54b267e8a974681012d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Initialization done.  <a href="#gac7e2936c9950b54b267e8a974681012d">More...</a><br/></td></tr>
<tr class="separator:gac7e2936c9950b54b267e8a974681012d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadd52dd222d3e9ddaae7418d3b5206a8e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gadd52dd222d3e9ddaae7418d3b5206a8e">XMIPI_RX_PHY_DLXSTATUS_REG_ULPS_OFFSET</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:gadd52dd222d3e9ddaae7418d3b5206a8e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for ULPS.  <a href="#gadd52dd222d3e9ddaae7418d3b5206a8e">More...</a><br/></td></tr>
<tr class="separator:gadd52dd222d3e9ddaae7418d3b5206a8e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga87a5f3801d85fe11d33349fe98c350b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#ga87a5f3801d85fe11d33349fe98c350b8">XMIPI_RX_PHY_DLXSTATUS_REG_MODE_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga87a5f3801d85fe11d33349fe98c350b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Modes.  <a href="#ga87a5f3801d85fe11d33349fe98c350b8">More...</a><br/></td></tr>
<tr class="separator:ga87a5f3801d85fe11d33349fe98c350b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Bitmask and offset of XMIPI_RX_PHY_HSSETTLE_REG_OFFSET register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpa8ddc39d86680d9c3be5e1214bac9bef"></a>This register is used to program the HS SETTLE register.</p>
<p>Default value is 135 + 10UI. </p>
</td></tr>
<tr class="memitem:gacd11b7eb937b614bc08120a16cc389ec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gacd11b7eb937b614bc08120a16cc389ec">XMIPI_RX_PHY_HSSETTLE_REG_TIMEOUT_MASK</a>&#160;&#160;&#160;0x1FF</td></tr>
<tr class="memdesc:gacd11b7eb937b614bc08120a16cc389ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">HS_SETTLE value.  <a href="#gacd11b7eb937b614bc08120a16cc389ec">More...</a><br/></td></tr>
<tr class="separator:gacd11b7eb937b614bc08120a16cc389ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabf5dce54c9db1dc7b447fe302ef80e37"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__rx__phy.html#gabf5dce54c9db1dc7b447fe302ef80e37">XMIPI_RX_PHY_HSSETTLE_REG_TIMEOUT_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:gabf5dce54c9db1dc7b447fe302ef80e37"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for HS_SETTLE.  <a href="#gabf5dce54c9db1dc7b447fe302ef80e37">More...</a><br/></td></tr>
<tr class="separator:gabf5dce54c9db1dc7b447fe302ef80e37"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="ga39c1f0241f05d6c2dd4e6d86a952f1f4"></a>
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          <td class="memname">#define XMIPI_RX_PHY_CLSTATUS_REG_ERRCTRL_MASK&#160;&#160;&#160;0x00000020</td>
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</div><div class="memdoc">

<p>Clock lane control error. </p>
<p>Only for RX </p>

</div>
</div>
<a class="anchor" id="gadbad3f46c30270a90ef31180b87631b8"></a>
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          <td class="memname">#define XMIPI_RX_PHY_CLSTATUS_REG_ERRCTRL_OFFSET&#160;&#160;&#160;5</td>
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<p>Bit offset for Control Error on Clock. </p>

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</div>
<a class="anchor" id="ga1004d17945d6005324cc685f1d7038ba"></a>
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          <td class="memname">#define XMIPI_RX_PHY_CLSTATUS_REG_INITDONE_MASK&#160;&#160;&#160;0x00000008</td>
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<p>Initialization done bit. </p>

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</div>
<a class="anchor" id="ga8d24544680c66148c097358ce8b33727"></a>
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          <td class="memname">#define XMIPI_RX_PHY_CLSTATUS_REG_INITDONE_OFFSET&#160;&#160;&#160;3</td>
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<p>Bit offset for Initialization Done. </p>

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<a class="anchor" id="ga0b072dcfbf16b94c76a98a422d609a8f"></a>
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          <td class="memname">#define XMIPI_RX_PHY_CLSTATUS_REG_MODE_MASK&#160;&#160;&#160;0x00000003</td>
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<p>Low, High, Esc mode. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga0c21c9093da86aa4159da50ded9b27c5">XMipi_Rx_Phy_GetClkLaneMode()</a>.</p>

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          <td class="memname">#define XMIPI_RX_PHY_CLSTATUS_REG_MODE_OFFSET&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit offset for Mode bits. </p>

</div>
</div>
<a class="anchor" id="ga6df3cddb2f8c6136193423656e1f8e54"></a>
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          <td class="memname">#define XMIPI_RX_PHY_CLSTATUS_REG_OFFSET&#160;&#160;&#160;0x00000018</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Clk lane PHY error Status Register. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#gafa9a8618d0efffc43b5001c4456dec8c">XMipi_Rx_Phy_GetClkLaneStatus()</a>, and <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="ga8db6d7f19e0431ee20321b3a635a2eca"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XMIPI_RX_PHY_CLSTATUS_REG_STOPSTATE_MASK&#160;&#160;&#160;0x00000010</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Clock lane stop state. </p>

</div>
</div>
<a class="anchor" id="ga6590b147d777602a6a0196968c3c65bd"></a>
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          <td class="memname">#define XMIPI_RX_PHY_CLSTATUS_REG_STOPSTATE_OFFSET&#160;&#160;&#160;4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit offset for Stop State on Clock. </p>

</div>
</div>
<a class="anchor" id="gac8c1a0b393d70ec50205cdff482db809"></a>
<div class="memitem">
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          <td class="memname">#define XMIPI_RX_PHY_CLSTATUS_REG_ULPS_MASK&#160;&#160;&#160;0x00000004</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Set in ULPS mode. </p>

</div>
</div>
<a class="anchor" id="ga276f3c942ce84cd5cce3340f986845ee"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XMIPI_RX_PHY_CLSTATUS_REG_ULPS_OFFSET&#160;&#160;&#160;2</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit offset for ULPS. </p>

</div>
</div>
<a class="anchor" id="ga0bf404750dfcaaefdd04d672d4a34ed2"></a>
<div class="memitem">
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          <td class="memname">#define XMIPI_RX_PHY_CTRL_REG_OFFSET&#160;&#160;&#160;0x00000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Control Register. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga0ac6ef589b022c2aa02bc6e234cc7433">XMipi_Rx_Phy_Activate()</a>, and <a class="el" href="group__mipi__rx__phy.html#ga52f42a2ed7b0acf4df27211b76708ab4">XMipi_Rx_Phy_Reset()</a>.</p>

</div>
</div>
<a class="anchor" id="gaec198293afc07be517b0ae8f92837d2c"></a>
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<div class="memproto">
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          <td class="memname">#define XMIPI_RX_PHY_CTRL_REG_PHYEN_MASK&#160;&#160;&#160;0x00000002</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Enable/Disable controller. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga0ac6ef589b022c2aa02bc6e234cc7433">XMipi_Rx_Phy_Activate()</a>.</p>

</div>
</div>
<a class="anchor" id="gaceeabb8c562fc7a8eedf90bbdd63b4c5"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XMIPI_RX_PHY_CTRL_REG_PHYEN_OFFSET&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit offset for PHY Enable. </p>

</div>
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<a class="anchor" id="ga99a08282c67427601f56d2ad64234ed6"></a>
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          <td class="memname">#define XMIPI_RX_PHY_CTRL_REG_SOFTRESET_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Soft Reset. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga52f42a2ed7b0acf4df27211b76708ab4">XMipi_Rx_Phy_Reset()</a>.</p>

</div>
</div>
<a class="anchor" id="gad2a85cb1a79f05bcfe068d2a5bb03233"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XMIPI_RX_PHY_CTRL_REG_SOFTRESET_OFFSET&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit offset for Soft Reset. </p>

</div>
</div>
<a class="anchor" id="ga7ca8cc7e96c85d80a747864154b5ffa0"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XMIPI_RX_PHY_DL0STATUS_REG_OFFSET&#160;&#160;&#160;0x0000001C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Data lane 0 PHY error Status Register. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#gac84fac31ab197bd3198dd11ca3896435">XMipi_Rx_Phy_ClearDataLane()</a>, <a class="el" href="group__mipi__rx__phy.html#gaed445ca4dc94ebbb7ed5b8035a7e914b">XMipi_Rx_Phy_GetDataLaneStatus()</a>, <a class="el" href="group__mipi__rx__phy.html#ga54671eb4258647bce4fc9cfe2cfa04b1">XMipi_Rx_Phy_GetDLCalibStatus()</a>, <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>, and <a class="el" href="group__mipi__rx__phy.html#ga451ed3af91fc85637ee4d1ab5de28da3">XMipi_Rx_Phy_GetPacketCount()</a>.</p>

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</div>
<a class="anchor" id="ga4d6de41a345ab9b0da5a07936f3a5d8a"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XMIPI_RX_PHY_DL1STATUS_REG_OFFSET&#160;&#160;&#160;0x00000020</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Data lane 1 PHY error Status Register. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="gaa7867d266b24387c2a89bb4c8e61306b"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XMIPI_RX_PHY_DL2STATUS_REG_OFFSET&#160;&#160;&#160;0x00000024</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Data lane 2 PHY error Status Register. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="gae602e9d94b72de6818a5b3f9e5b2bc82"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XMIPI_RX_PHY_DL3STATUS_REG_OFFSET&#160;&#160;&#160;0x00000028</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Data lane 3 PHY error Status Register. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="gae734cd3c1776660119a146b701d23039"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XMIPI_RX_PHY_DLXSTATUS_REG_CALIB_COMPLETE_MASK&#160;&#160;&#160;0x00000080</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Calib complete. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga54671eb4258647bce4fc9cfe2cfa04b1">XMipi_Rx_Phy_GetDLCalibStatus()</a>.</p>

</div>
</div>
<a class="anchor" id="ga4096f64ca0e39e289b86235fca5a037c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XMIPI_RX_PHY_DLXSTATUS_REG_CALIB_COMPLETE_OFFSET&#160;&#160;&#160;7</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit offset Calib complete. </p>

</div>
</div>
<a class="anchor" id="gae96674943b4c7ac2ef7f24e16d114f5e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XMIPI_RX_PHY_DLXSTATUS_REG_CALIB_STATUS_MASK&#160;&#160;&#160;0x00000100</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Calib status. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga54671eb4258647bce4fc9cfe2cfa04b1">XMipi_Rx_Phy_GetDLCalibStatus()</a>.</p>

</div>
</div>
<a class="anchor" id="ga8ab0be5e794c5b009c0fe65359589ac5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XMIPI_RX_PHY_DLXSTATUS_REG_CALIB_STATUS_OFFSET&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit offset calib status. </p>

</div>
</div>
<a class="anchor" id="ga193d957c5131a06eb4edf387464e8b23"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XMIPI_RX_PHY_DLXSTATUS_REG_ESCABRT_MASK&#160;&#160;&#160;0x00000020</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Set on Data Lane Esc timeout occurs. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#gac84fac31ab197bd3198dd11ca3896435">XMipi_Rx_Phy_ClearDataLane()</a>.</p>

</div>
</div>
<a class="anchor" id="ga7e3da7655adcb229ff3b0405df9fda81"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XMIPI_RX_PHY_DLXSTATUS_REG_ESCABRT_OFFSET&#160;&#160;&#160;5</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit offset for Escape Abort. </p>

</div>
</div>
<a class="anchor" id="ga80f071df87fac8194c77e2b17ca96f89"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XMIPI_RX_PHY_DLXSTATUS_REG_HSABRT_MASK&#160;&#160;&#160;0x00000010</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Set on Data Lane HS timeout. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#gac84fac31ab197bd3198dd11ca3896435">XMipi_Rx_Phy_ClearDataLane()</a>.</p>

</div>
</div>
<a class="anchor" id="ga848eac0c720848135936180fe5565fcf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XMIPI_RX_PHY_DLXSTATUS_REG_HSABRT_OFFSET&#160;&#160;&#160;4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit offset for High Speed Abort. </p>

</div>
</div>
<a class="anchor" id="ga375d4e779b8a019e67f724697281698f"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XMIPI_RX_PHY_DLXSTATUS_REG_INITDONE_MASK&#160;&#160;&#160;0x00000008</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Set after initialization. </p>

</div>
</div>
<a class="anchor" id="gac7e2936c9950b54b267e8a974681012d"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XMIPI_RX_PHY_DLXSTATUS_REG_INITDONE_OFFSET&#160;&#160;&#160;3</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit offset for Initialization done. </p>

</div>
</div>
<a class="anchor" id="ga8b20becb98cc3e299a6791e4a27165e5"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XMIPI_RX_PHY_DLXSTATUS_REG_MODE_MASK&#160;&#160;&#160;0x00000003</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Control Mode (Esc, Low, High) of Data Lane. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#gaca06750514da41ca96625aeebf2cee64">XMipi_Rx_Phy_GetDataLaneMode()</a>.</p>

</div>
</div>
<a class="anchor" id="ga87a5f3801d85fe11d33349fe98c350b8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XMIPI_RX_PHY_DLXSTATUS_REG_MODE_OFFSET&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit offset for Modes. </p>

</div>
</div>
<a class="anchor" id="ga998420b025e47070ad9a0d79ff4068b5"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XMIPI_RX_PHY_DLXSTATUS_REG_PACKCOUNT_OFFSET&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit offset packet count. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga451ed3af91fc85637ee4d1ab5de28da3">XMipi_Rx_Phy_GetPacketCount()</a>.</p>

</div>
</div>
<a class="anchor" id="ga57c759b34a6fc44b9b6bc969d84b949f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XMIPI_RX_PHY_DLXSTATUS_REG_PACKETCOUNT_MASK&#160;&#160;&#160;0xFFFF0000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Packet Count. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga451ed3af91fc85637ee4d1ab5de28da3">XMipi_Rx_Phy_GetPacketCount()</a>.</p>

</div>
</div>
<a class="anchor" id="ga9398f883326211edd06dc8d2c7bb1017"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XMIPI_RX_PHY_DLXSTATUS_REG_STOP_MASK&#160;&#160;&#160;0x00000040</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Stop State on data lane. </p>

</div>
</div>
<a class="anchor" id="ga8014b37b88e35bbf981445e019063b64"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XMIPI_RX_PHY_DLXSTATUS_REG_STOP_OFFSET&#160;&#160;&#160;6</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit offset for Stop State. </p>

</div>
</div>
<a class="anchor" id="ga17bd1c2c7ce0df5dbd19c46e6ea3feb4"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XMIPI_RX_PHY_DLXSTATUS_REG_ULPS_MASK&#160;&#160;&#160;0x00000004</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Set when MIPI_RX_PHY in ULPS mode. </p>

</div>
</div>
<a class="anchor" id="gadd52dd222d3e9ddaae7418d3b5206a8e"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XMIPI_RX_PHY_DLXSTATUS_REG_ULPS_OFFSET&#160;&#160;&#160;2</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit offset for ULPS. </p>

</div>
</div>
<a class="anchor" id="ga6ff6bab049c8e69e8ccbebc8b43b6eb7"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XMIPI_RX_PHY_ESCAPE_MODE&#160;&#160;&#160;2</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Lane in Escape Mode. </p>

</div>
</div>
<a class="anchor" id="ga1f2a7ab905af5a63575745e79fa1afef"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XMIPI_RX_PHY_ESCTIMEOUT_REG_OFFSET&#160;&#160;&#160;0x00000014</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Goto Stop state on timeout timer Register. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga60a0033eef09e3af1f3d38b2642bc990">XMipi_Rx_Phy_Configure()</a>, and <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="ga57f8374c40686716eb09f598db90d2d7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XMIPI_RX_PHY_ESCTIMEOUT_REG_VAL_MASK&#160;&#160;&#160;0xFFFFFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Escape Timout Value. </p>

</div>
</div>
<a class="anchor" id="ga79f52cbaa7e2faa9b99f6c7f1c901d41"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XMIPI_RX_PHY_ESCTIMEOUT_REG_VAL_OFFSET&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit offset for Escape Timeout. </p>

</div>
</div>
<a class="anchor" id="ga47f2481f1db47714aff2cff40ae1805a"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XMIPI_RX_PHY_H_</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Prevent circular inclusions by using protection macros. </p>

</div>
</div>
<a class="anchor" id="gaa79e40f54ad9778f3995f8ccfcb09fd8"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XMIPI_RX_PHY_HANDLE_CLKLANE&#160;&#160;&#160;5</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Handle for Clock Lane. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga60a0033eef09e3af1f3d38b2642bc990">XMipi_Rx_Phy_Configure()</a>, and <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="gafde9bac4868ce2d47e85c0de32532298"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XMIPI_RX_PHY_HANDLE_DLANE0&#160;&#160;&#160;6</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Handle for Data Lane 0. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga60a0033eef09e3af1f3d38b2642bc990">XMipi_Rx_Phy_Configure()</a>, and <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="gaf50cbba445009363e9a2821642d28984"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XMIPI_RX_PHY_HANDLE_DLANE1&#160;&#160;&#160;7</td>
        </tr>
      </table>
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<p>Handle for Data Lane 1. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga60a0033eef09e3af1f3d38b2642bc990">XMipi_Rx_Phy_Configure()</a>, and <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>.</p>

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<a class="anchor" id="gad3558fcc5200ad583a504c61ce1f0d15"></a>
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          <td class="memname">#define XMIPI_RX_PHY_HANDLE_DLANE2&#160;&#160;&#160;8</td>
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<p>Handle for Data Lane 2. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga60a0033eef09e3af1f3d38b2642bc990">XMipi_Rx_Phy_Configure()</a>, and <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>.</p>

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<a class="anchor" id="gaffb241b59b61b4dabff3a17173f34d5e"></a>
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          <td class="memname">#define XMIPI_RX_PHY_HANDLE_DLANE3&#160;&#160;&#160;9</td>
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<p>Handle for Data Lane 3. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga60a0033eef09e3af1f3d38b2642bc990">XMipi_Rx_Phy_Configure()</a>, and <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>.</p>

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<a class="anchor" id="gac915d728a8c6106c1deef751bdb2f93e"></a>
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          <td class="memname">#define XMIPI_RX_PHY_HANDLE_ESCTIMEOUT&#160;&#160;&#160;4</td>
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<p>Handle for Escape Timeout. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga60a0033eef09e3af1f3d38b2642bc990">XMipi_Rx_Phy_Configure()</a>, and <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>.</p>

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<a class="anchor" id="ga9ecbd14c9768eeff2b17f537d338f775"></a>
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          <td class="memname">#define XMIPI_RX_PHY_HANDLE_HSSETTLE0&#160;&#160;&#160;10</td>
        </tr>
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<p>Handle for HS SETTLE L0. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga60a0033eef09e3af1f3d38b2642bc990">XMipi_Rx_Phy_Configure()</a>, and <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>.</p>

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<a class="anchor" id="ga078f5a607947c32b21570f1640ea1a4a"></a>
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          <td class="memname">#define XMIPI_RX_PHY_HANDLE_HSSETTLE1&#160;&#160;&#160;11</td>
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<p>Handle for HS SETTLE L1. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga60a0033eef09e3af1f3d38b2642bc990">XMipi_Rx_Phy_Configure()</a>, and <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>.</p>

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<a class="anchor" id="ga568c5e242ff59d6b4f222f1642149406"></a>
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          <td class="memname">#define XMIPI_RX_PHY_HANDLE_HSSETTLE2&#160;&#160;&#160;12</td>
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<p>Handle for HS SETTLE L2. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga60a0033eef09e3af1f3d38b2642bc990">XMipi_Rx_Phy_Configure()</a>, and <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>.</p>

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<a class="anchor" id="ga473e22be644740e67566ce0ce2940124"></a>
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          <td class="memname">#define XMIPI_RX_PHY_HANDLE_HSSETTLE3&#160;&#160;&#160;13</td>
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<p>Handle for HS SETTLE L3. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga60a0033eef09e3af1f3d38b2642bc990">XMipi_Rx_Phy_Configure()</a>, and <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>.</p>

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<a class="anchor" id="ga72222b2af839769c09e80f143f2da026"></a>
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          <td class="memname">#define XMIPI_RX_PHY_HANDLE_HSTIMEOUT&#160;&#160;&#160;3</td>
        </tr>
      </table>
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<p>Handle for HS Timeout. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga60a0033eef09e3af1f3d38b2642bc990">XMipi_Rx_Phy_Configure()</a>, <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>, and <a class="el" href="group__mipi__rx__phy.html#ga73cfbe4a911c72bccdea37f91d5829d6">XMipi_Rx_Phy_SelfTest()</a>.</p>

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<a class="anchor" id="ga0972f732a6337d400b421b31a923bd89"></a>
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          <td class="memname">#define XMIPI_RX_PHY_HANDLE_IDELAY&#160;&#160;&#160;0</td>
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      </table>
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<p>Handle for IDELAY Reg. </p>

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<a class="anchor" id="gad4a4803f13f2ae21cfc4443b4f74ceb3"></a>
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          <td class="memname">#define XMIPI_RX_PHY_HANDLE_INIT_TIMER&#160;&#160;&#160;1</td>
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<p>Handle for Initialization Timer. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga60a0033eef09e3af1f3d38b2642bc990">XMipi_Rx_Phy_Configure()</a>, and <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>.</p>

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<a class="anchor" id="gabb969dbe56ae53bb6fec1916917be1b5"></a>
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          <td class="memname">#define XMIPI_RX_PHY_HANDLE_MAX&#160;&#160;&#160;14</td>
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<p>Upper Bound for XMIPI_RX_PHY_HANDLE. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga60a0033eef09e3af1f3d38b2642bc990">XMipi_Rx_Phy_Configure()</a>, and <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>.</p>

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<a class="anchor" id="ga0039d3d6608c07dff89ab4b92d2e4159"></a>
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          <td class="memname">#define XMIPI_RX_PHY_HANDLE_MIN&#160;&#160;&#160;0</td>
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<p>Lower Bound for XMIPI_RX_PHY_HANDLE. </p>

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          <td class="memname">#define XMIPI_RX_PHY_HANDLE_WAKEUP&#160;&#160;&#160;2</td>
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<p>Handle for Wakeup timer. </p>

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<a class="anchor" id="ga83b17604d921493045f62887dff773ca"></a>
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          <td class="memname">#define XMIPI_RX_PHY_HIGH_POWER_MODE&#160;&#160;&#160;1</td>
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<p>Lane in High Power Mode. </p>

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<a class="anchor" id="ga941337f26bc908ba365194c7d1e152ab"></a>
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          <td class="memname">#define XMIPI_RX_PHY_HSSETTLE0_REG_OFFSET&#160;&#160;&#160;0x00000030</td>
        </tr>
      </table>
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<p>HS Settle Register L0. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga60a0033eef09e3af1f3d38b2642bc990">XMipi_Rx_Phy_Configure()</a>, and <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>.</p>

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<a class="anchor" id="ga811dbc44fe9d3b4dc258652de27d661c"></a>
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          <td class="memname">#define XMIPI_RX_PHY_HSSETTLE1_REG_OFFSET&#160;&#160;&#160;0x00000048</td>
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<p>HS Settle Register L1. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga60a0033eef09e3af1f3d38b2642bc990">XMipi_Rx_Phy_Configure()</a>, and <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>.</p>

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<a class="anchor" id="ga6c837a9e2b95486169ad376478bfc14e"></a>
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          <td class="memname">#define XMIPI_RX_PHY_HSSETTLE2_REG_OFFSET&#160;&#160;&#160;0x0000004C</td>
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<p>HS Settle Register L2. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga60a0033eef09e3af1f3d38b2642bc990">XMipi_Rx_Phy_Configure()</a>, and <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>.</p>

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<a class="anchor" id="ga832f2a3a308197b899ba0f7d0b33e908"></a>
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          <td class="memname">#define XMIPI_RX_PHY_HSSETTLE3_REG_OFFSET&#160;&#160;&#160;0x00000050</td>
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<p>HS Settle Register L3. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga60a0033eef09e3af1f3d38b2642bc990">XMipi_Rx_Phy_Configure()</a>, and <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>.</p>

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<a class="anchor" id="gacd11b7eb937b614bc08120a16cc389ec"></a>
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          <td class="memname">#define XMIPI_RX_PHY_HSSETTLE_REG_TIMEOUT_MASK&#160;&#160;&#160;0x1FF</td>
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<p>HS_SETTLE value. </p>

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<a class="anchor" id="gabf5dce54c9db1dc7b447fe302ef80e37"></a>
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          <td class="memname">#define XMIPI_RX_PHY_HSSETTLE_REG_TIMEOUT_OFFSET&#160;&#160;&#160;0</td>
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<p>Bit offset for HS_SETTLE. </p>

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<a class="anchor" id="gace1a808a2597c0a1395016ec4de67d8a"></a>
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          <td class="memname">#define XMIPI_RX_PHY_HSTIMEOUT_REG_OFFSET&#160;&#160;&#160;0x00000010</td>
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<p>Watchdog timeout in HS mode Register. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga60a0033eef09e3af1f3d38b2642bc990">XMipi_Rx_Phy_Configure()</a>, and <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>.</p>

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<a class="anchor" id="ga2b315903c952abd8e09c802a1a6be4c3"></a>
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          <td class="memname">#define XMIPI_RX_PHY_HSTIMEOUT_REG_TIMEOUT_MASK&#160;&#160;&#160;0xFFFFFFFF</td>
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<p>HS_RX_TIMEOUT Received. </p>

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<a class="anchor" id="gadec1619af7a2de87d591812729bc52d1"></a>
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          <td class="memname">#define XMIPI_RX_PHY_HSTIMEOUT_REG_TIMEOUT_OFFSET&#160;&#160;&#160;0</td>
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<p>Bit offset for Timeout. </p>

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<a class="anchor" id="ga10de00dc29c09ca2f4cd07b791947303"></a>
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          <td class="memname">#define XMIPI_RX_PHY_HW_H_</td>
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<p>Prevent circular inclusions by using protection macros. </p>

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<a class="anchor" id="gab750cb7ee4477ebf02dee74a7e912949"></a>
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          <td class="memname">#define XMIPI_RX_PHY_INIT_REG_VAL_MASK&#160;&#160;&#160;0xFFFFFFFF</td>
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<p>Init Timer value in ns. </p>

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<a class="anchor" id="ga02c8e40953545ada2100d4431ffe3061"></a>
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          <td class="memname">#define XMIPI_RX_PHY_INIT_REG_VAL_OFFSET&#160;&#160;&#160;0</td>
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<p>Bit offset for Init Timer. </p>

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<a class="anchor" id="ga5d73b98adf4b04216bb1742cc3ad92d6"></a>
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          <td class="memname">#define XMIPI_RX_PHY_INIT_TIMER_REG_OFFSET&#160;&#160;&#160;0x00000008</td>
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<p>Initialization Timer Register. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga60a0033eef09e3af1f3d38b2642bc990">XMipi_Rx_Phy_Configure()</a>, and <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>.</p>

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<a class="anchor" id="ga12575a833db166780c85a10a45b142c8"></a>
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          <td class="memname">#define XMIPI_RX_PHY_LOW_POWER_MODE&#160;&#160;&#160;0</td>
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<p>Lane in Low Power Mode. </p>

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<a class="anchor" id="ga91cf5eb7c138a6a6f2bc4f05be160ea8"></a>
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          <td class="memname">#define XMIPI_RX_PHY_MAX_LANES_V10&#160;&#160;&#160;4</td>
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<p>V1.0 supports 4 Lanes. </p>

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<a class="anchor" id="ga34e4e2c11b6b212760e6e372cccde8e1"></a>
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          <td class="memname">#define XMIPI_RX_PHY_MODE_MAX&#160;&#160;&#160;2</td>
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<p>Upper Limit for mode. </p>

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<a class="anchor" id="ga0f33ed842e29cb278f24a1c7d661aaa9"></a>
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          <td class="memname">#define XMIPI_RX_PHY_MODE_MIN&#160;&#160;&#160;0</td>
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<p>Lower limit for Mode. </p>

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<a class="anchor" id="gaf427e80f588294f6bd021db121fc76fd"></a>
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          <td class="memname">#define XMIPI_RX_PHY_VERSION_REG_OFFSET&#160;&#160;&#160;0x00000004</td>
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<p>Core Version Register. </p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#gafeeea99a20ac3bb4b3c05f64064feb86">XMipi_Rx_Phy_GetVersionReg()</a>.</p>

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<h2 class="groupheader">Function Documentation</h2>
<a class="anchor" id="ga0ac6ef589b022c2aa02bc6e234cc7433"></a>
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          <td class="memname">void XMipi_Rx_Phy_Activate </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Flag</em>&#160;</td>
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          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function is used to enable or disable the Mipi_Rx_Phy core. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___rx___phy.html" title="The Xmipi_rx_phy Controller driver instance data. ">XMipi_Rx_Phy</a> instance to operate on. </td></tr>
    <tr><td class="paramname">Flag</td><td>denoting whether to enable or disable the Mipi_Rx_Phy core</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___rx___phy___config.html#a638141292da08ecc26f4d1ebca26a005">XMipi_Rx_Phy_Config::BaseAddr</a>, <a class="el" href="struct_x_mipi___rx___phy.html#aacb9702cb804f802478eb4d8c16fca38">XMipi_Rx_Phy::Config</a>, <a class="el" href="struct_x_mipi___rx___phy___config.html#a75232bef192fd87b24590e009404289d">XMipi_Rx_Phy_Config::IsRegisterPresent</a>, <a class="el" href="group__mipi__rx__phy.html#ga0bf404750dfcaaefdd04d672d4a34ed2">XMIPI_RX_PHY_CTRL_REG_OFFSET</a>, and <a class="el" href="group__mipi__rx__phy.html#gaec198293afc07be517b0ae8f92837d2c">XMIPI_RX_PHY_CTRL_REG_PHYEN_MASK</a>.</p>

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          <td class="memname">u32 XMipi_Rx_Phy_CfgInitialize </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___rx___phy___config.html">XMipi_Rx_Phy_Config</a> *&#160;</td>
          <td class="paramname"><em>CfgPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>EffectiveAddr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Initialize the <a class="el" href="struct_x_mipi___rx___phy.html" title="The Xmipi_rx_phy Controller driver instance data. ">XMipi_Rx_Phy</a> instance provided by the caller based on the given Config structure. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___rx___phy.html" title="The Xmipi_rx_phy Controller driver instance data. ">XMipi_Rx_Phy</a> instance to operate on. </td></tr>
    <tr><td class="paramname">CfgPtr</td><td>is the device configuration structure containing information about a specific Mipi_Rx_Phy instance. </td></tr>
    <tr><td class="paramname">EffectiveAddr</td><td>is the base address of the device. If address translation is being used, then this parameter must reflect the virtual base address. Otherwise, the physical address should be used. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS Initialization was successful.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___rx___phy___config.html#a638141292da08ecc26f4d1ebca26a005">XMipi_Rx_Phy_Config::BaseAddr</a>, <a class="el" href="struct_x_mipi___rx___phy.html#aacb9702cb804f802478eb4d8c16fca38">XMipi_Rx_Phy::Config</a>, and <a class="el" href="struct_x_mipi___rx___phy.html#abe4cd40c02e009828af28a8482bdbaf9">XMipi_Rx_Phy::IsReady</a>.</p>

<p>Referenced by <a class="el" href="xmipi__rx__phy__example__selftest_8c.html#a6dc882f61ad6323877a35d7bc3c3f6b5">Mipi_Rx_PhySelfTestExample()</a>.</p>

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          <td class="memname">void XMipi_Rx_Phy_ClearDataLane </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>DataLane</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Mask</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This is used to clear the Abort Error (Escape or High Speed) bits in the Data Lane 0 through 3. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___rx___phy.html" title="The Xmipi_rx_phy Controller driver instance data. ">XMipi_Rx_Phy</a> instance to operate on. </td></tr>
    <tr><td class="paramname">DataLane</td><td>represents which Data Lane to act upon </td></tr>
    <tr><td class="paramname">Mask</td><td>contains information about which bits to reset</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___rx___phy___config.html#a638141292da08ecc26f4d1ebca26a005">XMipi_Rx_Phy_Config::BaseAddr</a>, <a class="el" href="struct_x_mipi___rx___phy.html#aacb9702cb804f802478eb4d8c16fca38">XMipi_Rx_Phy::Config</a>, <a class="el" href="struct_x_mipi___rx___phy___config.html#a75232bef192fd87b24590e009404289d">XMipi_Rx_Phy_Config::IsRegisterPresent</a>, <a class="el" href="group__mipi__rx__phy.html#ga7ca8cc7e96c85d80a747864154b5ffa0">XMIPI_RX_PHY_DL0STATUS_REG_OFFSET</a>, <a class="el" href="group__mipi__rx__phy.html#ga193d957c5131a06eb4edf387464e8b23">XMIPI_RX_PHY_DLXSTATUS_REG_ESCABRT_MASK</a>, and <a class="el" href="group__mipi__rx__phy.html#ga80f071df87fac8194c77e2b17ca96f89">XMIPI_RX_PHY_DLXSTATUS_REG_HSABRT_MASK</a>.</p>

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          <td class="memname">u32 XMipi_Rx_Phy_Configure </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Handle</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Value</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Configure the registers of the Mipi_Rx_Phy instance. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___rx___phy.html" title="The Xmipi_rx_phy Controller driver instance data. ">XMipi_Rx_Phy</a> instance to operate on. </td></tr>
    <tr><td class="paramname">Handle</td><td>to one of the registers to be configured </td></tr>
    <tr><td class="paramname">Value</td><td>to be set for the particular Handle of the Mipi_Rx_Phy instance</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS on successful register update.</li>
<li>XST_FAILURE If incorrect handle was passed</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>There is a limit on the minimum and maximum values of the HS Timeout register. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___rx___phy.html#aacb9702cb804f802478eb4d8c16fca38">XMipi_Rx_Phy::Config</a>, <a class="el" href="struct_x_mipi___rx___phy___config.html#a983935852df64386544e48ba4be1ad10">XMipi_Rx_Phy_Config::EnableTimeOutRegs</a>, <a class="el" href="struct_x_mipi___rx___phy___config.html#a4cb2986e0b22c7b0c06bc5d95f51159c">XMipi_Rx_Phy_Config::IsDphy</a>, <a class="el" href="struct_x_mipi___rx___phy___config.html#a75232bef192fd87b24590e009404289d">XMipi_Rx_Phy_Config::IsRegisterPresent</a>, <a class="el" href="group__mipi__rx__phy.html#ga1f2a7ab905af5a63575745e79fa1afef">XMIPI_RX_PHY_ESCTIMEOUT_REG_OFFSET</a>, <a class="el" href="group__mipi__rx__phy.html#gaa79e40f54ad9778f3995f8ccfcb09fd8">XMIPI_RX_PHY_HANDLE_CLKLANE</a>, <a class="el" href="group__mipi__rx__phy.html#gafde9bac4868ce2d47e85c0de32532298">XMIPI_RX_PHY_HANDLE_DLANE0</a>, <a class="el" href="group__mipi__rx__phy.html#gaf50cbba445009363e9a2821642d28984">XMIPI_RX_PHY_HANDLE_DLANE1</a>, <a class="el" href="group__mipi__rx__phy.html#gad3558fcc5200ad583a504c61ce1f0d15">XMIPI_RX_PHY_HANDLE_DLANE2</a>, <a class="el" href="group__mipi__rx__phy.html#gaffb241b59b61b4dabff3a17173f34d5e">XMIPI_RX_PHY_HANDLE_DLANE3</a>, <a class="el" href="group__mipi__rx__phy.html#gac915d728a8c6106c1deef751bdb2f93e">XMIPI_RX_PHY_HANDLE_ESCTIMEOUT</a>, <a class="el" href="group__mipi__rx__phy.html#ga9ecbd14c9768eeff2b17f537d338f775">XMIPI_RX_PHY_HANDLE_HSSETTLE0</a>, <a class="el" href="group__mipi__rx__phy.html#ga078f5a607947c32b21570f1640ea1a4a">XMIPI_RX_PHY_HANDLE_HSSETTLE1</a>, <a class="el" href="group__mipi__rx__phy.html#ga568c5e242ff59d6b4f222f1642149406">XMIPI_RX_PHY_HANDLE_HSSETTLE2</a>, <a class="el" href="group__mipi__rx__phy.html#ga473e22be644740e67566ce0ce2940124">XMIPI_RX_PHY_HANDLE_HSSETTLE3</a>, <a class="el" href="group__mipi__rx__phy.html#ga72222b2af839769c09e80f143f2da026">XMIPI_RX_PHY_HANDLE_HSTIMEOUT</a>, <a class="el" href="group__mipi__rx__phy.html#gad4a4803f13f2ae21cfc4443b4f74ceb3">XMIPI_RX_PHY_HANDLE_INIT_TIMER</a>, <a class="el" href="group__mipi__rx__phy.html#gabb969dbe56ae53bb6fec1916917be1b5">XMIPI_RX_PHY_HANDLE_MAX</a>, <a class="el" href="group__mipi__rx__phy.html#ga941337f26bc908ba365194c7d1e152ab">XMIPI_RX_PHY_HSSETTLE0_REG_OFFSET</a>, <a class="el" href="group__mipi__rx__phy.html#ga811dbc44fe9d3b4dc258652de27d661c">XMIPI_RX_PHY_HSSETTLE1_REG_OFFSET</a>, <a class="el" href="group__mipi__rx__phy.html#ga6c837a9e2b95486169ad376478bfc14e">XMIPI_RX_PHY_HSSETTLE2_REG_OFFSET</a>, <a class="el" href="group__mipi__rx__phy.html#ga832f2a3a308197b899ba0f7d0b33e908">XMIPI_RX_PHY_HSSETTLE3_REG_OFFSET</a>, <a class="el" href="group__mipi__rx__phy.html#gace1a808a2597c0a1395016ec4de67d8a">XMIPI_RX_PHY_HSTIMEOUT_REG_OFFSET</a>, and <a class="el" href="group__mipi__rx__phy.html#ga5d73b98adf4b04216bb1742cc3ad92d6">XMIPI_RX_PHY_INIT_TIMER_REG_OFFSET</a>.</p>

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          <td class="memname">u32 XMipi_Rx_Phy_GetClkLaneMode </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This is used to get specific Lane mode information about Clock Lane. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___rx___phy.html" title="The Xmipi_rx_phy Controller driver instance data. ">XMipi_Rx_Phy</a> instance to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Bitmask containing mode in which the Clock Lane in Mipi_Rx_Phy is in.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___rx___phy.html#aacb9702cb804f802478eb4d8c16fca38">XMipi_Rx_Phy::Config</a>, <a class="el" href="struct_x_mipi___rx___phy___config.html#a4cb2986e0b22c7b0c06bc5d95f51159c">XMipi_Rx_Phy_Config::IsDphy</a>, <a class="el" href="struct_x_mipi___rx___phy___config.html#a75232bef192fd87b24590e009404289d">XMipi_Rx_Phy_Config::IsRegisterPresent</a>, <a class="el" href="group__mipi__rx__phy.html#ga0b072dcfbf16b94c76a98a422d609a8f">XMIPI_RX_PHY_CLSTATUS_REG_MODE_MASK</a>, and <a class="el" href="group__mipi__rx__phy.html#gafa9a8618d0efffc43b5001c4456dec8c">XMipi_Rx_Phy_GetClkLaneStatus()</a>.</p>

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          <td class="memname">u32 XMipi_Rx_Phy_GetClkLaneStatus </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This is used to get information about Clock Lane status. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___rx___phy.html" title="The Xmipi_rx_phy Controller driver instance data. ">XMipi_Rx_Phy</a> instance to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Bitmask containing which of the events have occured along with the mode of the Clock Lane in Phy</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___rx___phy___config.html#a638141292da08ecc26f4d1ebca26a005">XMipi_Rx_Phy_Config::BaseAddr</a>, <a class="el" href="struct_x_mipi___rx___phy.html#aacb9702cb804f802478eb4d8c16fca38">XMipi_Rx_Phy::Config</a>, <a class="el" href="struct_x_mipi___rx___phy___config.html#a4cb2986e0b22c7b0c06bc5d95f51159c">XMipi_Rx_Phy_Config::IsDphy</a>, <a class="el" href="struct_x_mipi___rx___phy___config.html#a75232bef192fd87b24590e009404289d">XMipi_Rx_Phy_Config::IsRegisterPresent</a>, and <a class="el" href="group__mipi__rx__phy.html#ga6df3cddb2f8c6136193423656e1f8e54">XMIPI_RX_PHY_CLSTATUS_REG_OFFSET</a>.</p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga0c21c9093da86aa4159da50ded9b27c5">XMipi_Rx_Phy_GetClkLaneMode()</a>.</p>

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          <td class="memname">u32 XMipi_Rx_Phy_GetDataLaneMode </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>DataLane</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This is used to get specfic Lane mode information about a Data Lane. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___rx___phy.html" title="The Xmipi_rx_phy Controller driver instance data. ">XMipi_Rx_Phy</a> instance to operate on. </td></tr>
    <tr><td class="paramname">DataLane</td><td>for which the mode info is requested.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Bitmask containing mode in which the Data Lane in Mipi_Rx_Phy is in.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___rx___phy.html#aacb9702cb804f802478eb4d8c16fca38">XMipi_Rx_Phy::Config</a>, <a class="el" href="struct_x_mipi___rx___phy___config.html#a75232bef192fd87b24590e009404289d">XMipi_Rx_Phy_Config::IsRegisterPresent</a>, <a class="el" href="group__mipi__rx__phy.html#ga8b20becb98cc3e299a6791e4a27165e5">XMIPI_RX_PHY_DLXSTATUS_REG_MODE_MASK</a>, and <a class="el" href="group__mipi__rx__phy.html#gaed445ca4dc94ebbb7ed5b8035a7e914b">XMipi_Rx_Phy_GetDataLaneStatus()</a>.</p>

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          <td class="memname">u32 XMipi_Rx_Phy_GetDataLaneStatus </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>DataLane</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This is used to get information about a Data Lane status. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___rx___phy.html" title="The Xmipi_rx_phy Controller driver instance data. ">XMipi_Rx_Phy</a> instance to operate on. </td></tr>
    <tr><td class="paramname">DataLane</td><td>for which the status is sought for.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Bitmask containing which of the events have occured along with the mode of the Data Lane in Phy</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___rx___phy___config.html#a638141292da08ecc26f4d1ebca26a005">XMipi_Rx_Phy_Config::BaseAddr</a>, <a class="el" href="struct_x_mipi___rx___phy.html#aacb9702cb804f802478eb4d8c16fca38">XMipi_Rx_Phy::Config</a>, <a class="el" href="struct_x_mipi___rx___phy___config.html#a75232bef192fd87b24590e009404289d">XMipi_Rx_Phy_Config::IsRegisterPresent</a>, and <a class="el" href="group__mipi__rx__phy.html#ga7ca8cc7e96c85d80a747864154b5ffa0">XMIPI_RX_PHY_DL0STATUS_REG_OFFSET</a>.</p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#gaca06750514da41ca96625aeebf2cee64">XMipi_Rx_Phy_GetDataLaneMode()</a>.</p>

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          <td class="memname">u8 XMipi_Rx_Phy_GetDLCalibStatus </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>DataLane</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This is used to get Data Lane Calibration status. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___rx___phy.html" title="The Xmipi_rx_phy Controller driver instance data. ">XMipi_Rx_Phy</a> instance to operate on. </td></tr>
    <tr><td class="paramname">DataLane</td><td>for which the calib status is sought for.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>XST_SUCCESS - Calibration Complete, Calibration packet received XST_NO_DATA - Calibration Complete, Calibration packet is not received XST_FAILURE - Calibration failed</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___rx___phy___config.html#a638141292da08ecc26f4d1ebca26a005">XMipi_Rx_Phy_Config::BaseAddr</a>, <a class="el" href="struct_x_mipi___rx___phy.html#aacb9702cb804f802478eb4d8c16fca38">XMipi_Rx_Phy::Config</a>, <a class="el" href="struct_x_mipi___rx___phy___config.html#a75232bef192fd87b24590e009404289d">XMipi_Rx_Phy_Config::IsRegisterPresent</a>, <a class="el" href="group__mipi__rx__phy.html#ga7ca8cc7e96c85d80a747864154b5ffa0">XMIPI_RX_PHY_DL0STATUS_REG_OFFSET</a>, <a class="el" href="group__mipi__rx__phy.html#gae734cd3c1776660119a146b701d23039">XMIPI_RX_PHY_DLXSTATUS_REG_CALIB_COMPLETE_MASK</a>, and <a class="el" href="group__mipi__rx__phy.html#gae96674943b4c7ac2ef7f24e16d114f5e">XMIPI_RX_PHY_DLXSTATUS_REG_CALIB_STATUS_MASK</a>.</p>

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          <td class="memname">u32 XMipi_Rx_Phy_GetInfo </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Handle</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>Get information stored in the Mipi_Rx_Phy instance based on the handle passed. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___rx___phy.html" title="The Xmipi_rx_phy Controller driver instance data. ">XMipi_Rx_Phy</a> instance to operate on. </td></tr>
    <tr><td class="paramname">Handle</td><td>to one of the registers to be configured</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The value stored in the corresponding register</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___rx___phy.html#aacb9702cb804f802478eb4d8c16fca38">XMipi_Rx_Phy::Config</a>, <a class="el" href="struct_x_mipi___rx___phy___config.html#a983935852df64386544e48ba4be1ad10">XMipi_Rx_Phy_Config::EnableTimeOutRegs</a>, <a class="el" href="struct_x_mipi___rx___phy___config.html#a9348f07e9115bbb5a18b057917414ad0">XMipi_Rx_Phy_Config::EscTimeout</a>, <a class="el" href="struct_x_mipi___rx___phy___config.html#a05e041c93ffdd9e6728c70cc0cd77faf">XMipi_Rx_Phy_Config::HSTimeOut</a>, <a class="el" href="struct_x_mipi___rx___phy___config.html#a4cb2986e0b22c7b0c06bc5d95f51159c">XMipi_Rx_Phy_Config::IsDphy</a>, <a class="el" href="struct_x_mipi___rx___phy___config.html#a75232bef192fd87b24590e009404289d">XMipi_Rx_Phy_Config::IsRegisterPresent</a>, <a class="el" href="struct_x_mipi___rx___phy___config.html#a4b2de91b88796e464b637910c8ae2989">XMipi_Rx_Phy_Config::MaxLanesPresent</a>, <a class="el" href="group__mipi__rx__phy.html#ga6df3cddb2f8c6136193423656e1f8e54">XMIPI_RX_PHY_CLSTATUS_REG_OFFSET</a>, <a class="el" href="group__mipi__rx__phy.html#ga7ca8cc7e96c85d80a747864154b5ffa0">XMIPI_RX_PHY_DL0STATUS_REG_OFFSET</a>, <a class="el" href="group__mipi__rx__phy.html#ga4d6de41a345ab9b0da5a07936f3a5d8a">XMIPI_RX_PHY_DL1STATUS_REG_OFFSET</a>, <a class="el" href="group__mipi__rx__phy.html#gaa7867d266b24387c2a89bb4c8e61306b">XMIPI_RX_PHY_DL2STATUS_REG_OFFSET</a>, <a class="el" href="group__mipi__rx__phy.html#gae602e9d94b72de6818a5b3f9e5b2bc82">XMIPI_RX_PHY_DL3STATUS_REG_OFFSET</a>, <a class="el" href="group__mipi__rx__phy.html#ga1f2a7ab905af5a63575745e79fa1afef">XMIPI_RX_PHY_ESCTIMEOUT_REG_OFFSET</a>, <a class="el" href="group__mipi__rx__phy.html#gaa79e40f54ad9778f3995f8ccfcb09fd8">XMIPI_RX_PHY_HANDLE_CLKLANE</a>, <a class="el" href="group__mipi__rx__phy.html#gafde9bac4868ce2d47e85c0de32532298">XMIPI_RX_PHY_HANDLE_DLANE0</a>, <a class="el" href="group__mipi__rx__phy.html#gaf50cbba445009363e9a2821642d28984">XMIPI_RX_PHY_HANDLE_DLANE1</a>, <a class="el" href="group__mipi__rx__phy.html#gad3558fcc5200ad583a504c61ce1f0d15">XMIPI_RX_PHY_HANDLE_DLANE2</a>, <a class="el" href="group__mipi__rx__phy.html#gaffb241b59b61b4dabff3a17173f34d5e">XMIPI_RX_PHY_HANDLE_DLANE3</a>, <a class="el" href="group__mipi__rx__phy.html#gac915d728a8c6106c1deef751bdb2f93e">XMIPI_RX_PHY_HANDLE_ESCTIMEOUT</a>, <a class="el" href="group__mipi__rx__phy.html#ga9ecbd14c9768eeff2b17f537d338f775">XMIPI_RX_PHY_HANDLE_HSSETTLE0</a>, <a class="el" href="group__mipi__rx__phy.html#ga078f5a607947c32b21570f1640ea1a4a">XMIPI_RX_PHY_HANDLE_HSSETTLE1</a>, <a class="el" href="group__mipi__rx__phy.html#ga568c5e242ff59d6b4f222f1642149406">XMIPI_RX_PHY_HANDLE_HSSETTLE2</a>, <a class="el" href="group__mipi__rx__phy.html#ga473e22be644740e67566ce0ce2940124">XMIPI_RX_PHY_HANDLE_HSSETTLE3</a>, <a class="el" href="group__mipi__rx__phy.html#ga72222b2af839769c09e80f143f2da026">XMIPI_RX_PHY_HANDLE_HSTIMEOUT</a>, <a class="el" href="group__mipi__rx__phy.html#gad4a4803f13f2ae21cfc4443b4f74ceb3">XMIPI_RX_PHY_HANDLE_INIT_TIMER</a>, <a class="el" href="group__mipi__rx__phy.html#gabb969dbe56ae53bb6fec1916917be1b5">XMIPI_RX_PHY_HANDLE_MAX</a>, <a class="el" href="group__mipi__rx__phy.html#ga941337f26bc908ba365194c7d1e152ab">XMIPI_RX_PHY_HSSETTLE0_REG_OFFSET</a>, <a class="el" href="group__mipi__rx__phy.html#ga811dbc44fe9d3b4dc258652de27d661c">XMIPI_RX_PHY_HSSETTLE1_REG_OFFSET</a>, <a class="el" href="group__mipi__rx__phy.html#ga6c837a9e2b95486169ad376478bfc14e">XMIPI_RX_PHY_HSSETTLE2_REG_OFFSET</a>, <a class="el" href="group__mipi__rx__phy.html#ga832f2a3a308197b899ba0f7d0b33e908">XMIPI_RX_PHY_HSSETTLE3_REG_OFFSET</a>, <a class="el" href="group__mipi__rx__phy.html#gace1a808a2597c0a1395016ec4de67d8a">XMIPI_RX_PHY_HSTIMEOUT_REG_OFFSET</a>, and <a class="el" href="group__mipi__rx__phy.html#ga5d73b98adf4b04216bb1742cc3ad92d6">XMIPI_RX_PHY_INIT_TIMER_REG_OFFSET</a>.</p>

<p>Referenced by <a class="el" href="group__mipi__rx__phy.html#ga73cfbe4a911c72bccdea37f91d5829d6">XMipi_Rx_Phy_SelfTest()</a>.</p>

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          <td class="memname">u16 XMipi_Rx_Phy_GetPacketCount </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>DataLane</em>&#160;</td>
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          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This is used to get count of packets received on each lane. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___rx___phy.html" title="The Xmipi_rx_phy Controller driver instance data. ">XMipi_Rx_Phy</a> instance to operate on. </td></tr>
    <tr><td class="paramname">DataLane</td><td>for which the mode info is requested.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Bitmask containing mode in which the Data Lane in Mipi_Rx_Phy is in.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___rx___phy___config.html#a638141292da08ecc26f4d1ebca26a005">XMipi_Rx_Phy_Config::BaseAddr</a>, <a class="el" href="struct_x_mipi___rx___phy.html#aacb9702cb804f802478eb4d8c16fca38">XMipi_Rx_Phy::Config</a>, <a class="el" href="struct_x_mipi___rx___phy___config.html#a75232bef192fd87b24590e009404289d">XMipi_Rx_Phy_Config::IsRegisterPresent</a>, <a class="el" href="group__mipi__rx__phy.html#ga7ca8cc7e96c85d80a747864154b5ffa0">XMIPI_RX_PHY_DL0STATUS_REG_OFFSET</a>, <a class="el" href="group__mipi__rx__phy.html#ga998420b025e47070ad9a0d79ff4068b5">XMIPI_RX_PHY_DLXSTATUS_REG_PACKCOUNT_OFFSET</a>, and <a class="el" href="group__mipi__rx__phy.html#ga57c759b34a6fc44b9b6bc969d84b949f">XMIPI_RX_PHY_DLXSTATUS_REG_PACKETCOUNT_MASK</a>.</p>

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          <td class="memname">u8 XMipi_Rx_Phy_GetRegIntfcPresent </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>Get if register interface is present from the config structure for specified Mipi_Rx_Phy instance. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___rx___phy.html" title="The Xmipi_rx_phy Controller driver instance data. ">XMipi_Rx_Phy</a> instance to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>1 if register interface is present</li>
<li>0 if register interface is absent</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___rx___phy.html#aacb9702cb804f802478eb4d8c16fca38">XMipi_Rx_Phy::Config</a>, and <a class="el" href="struct_x_mipi___rx___phy___config.html#a75232bef192fd87b24590e009404289d">XMipi_Rx_Phy_Config::IsRegisterPresent</a>.</p>

<p>Referenced by <a class="el" href="xmipi__rx__phy__example__selftest_8c.html#a6dc882f61ad6323877a35d7bc3c3f6b5">Mipi_Rx_PhySelfTestExample()</a>.</p>

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          <td class="memname">u32 XMipi_Rx_Phy_GetVersionReg </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This is used to get Mipi_Rx_Phy Version. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___rx___phy.html" title="The Xmipi_rx_phy Controller driver instance data. ">XMipi_Rx_Phy</a> instance to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Returns major and minor Version number of this Mipi_Rx_Phy IP</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___rx___phy___config.html#a638141292da08ecc26f4d1ebca26a005">XMipi_Rx_Phy_Config::BaseAddr</a>, <a class="el" href="struct_x_mipi___rx___phy.html#aacb9702cb804f802478eb4d8c16fca38">XMipi_Rx_Phy::Config</a>, <a class="el" href="struct_x_mipi___rx___phy___config.html#a75232bef192fd87b24590e009404289d">XMipi_Rx_Phy_Config::IsRegisterPresent</a>, and <a class="el" href="group__mipi__rx__phy.html#gaf427e80f588294f6bd021db121fc76fd">XMIPI_RX_PHY_VERSION_REG_OFFSET</a>.</p>

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          <td class="memname"><a class="el" href="struct_x_mipi___rx___phy___config.html">XMipi_Rx_Phy_Config</a> * XMipi_Rx_Phy_LookupConfig </td>
          <td>(</td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>BaseAddress</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>Look up the hardware configuration for a device instance. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the BaseAddress of the device to lookup for</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The reference to the configuration record in the configuration table (in xmipi_rx_phy_g.c) corresponding to the BaseAddr or if not found,a NULL pointer is returned.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

<p>Referenced by <a class="el" href="xmipi__rx__phy__example__selftest_8c.html#a6dc882f61ad6323877a35d7bc3c3f6b5">Mipi_Rx_PhySelfTestExample()</a>.</p>

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          <td class="memname">void XMipi_Rx_Phy_Reset </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This is used to do a soft reset of the Mipi_Rx_Phy IP instance. </p>
<p>The reset takes approx 20 core clock cycles to become effective.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___rx___phy.html" title="The Xmipi_rx_phy Controller driver instance data. ">XMipi_Rx_Phy</a> instance to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___rx___phy.html#aacb9702cb804f802478eb4d8c16fca38">XMipi_Rx_Phy::Config</a>, <a class="el" href="struct_x_mipi___rx___phy.html#abe4cd40c02e009828af28a8482bdbaf9">XMipi_Rx_Phy::IsReady</a>, <a class="el" href="struct_x_mipi___rx___phy___config.html#a75232bef192fd87b24590e009404289d">XMipi_Rx_Phy_Config::IsRegisterPresent</a>, <a class="el" href="group__mipi__rx__phy.html#ga0bf404750dfcaaefdd04d672d4a34ed2">XMIPI_RX_PHY_CTRL_REG_OFFSET</a>, and <a class="el" href="group__mipi__rx__phy.html#ga99a08282c67427601f56d2ad64234ed6">XMIPI_RX_PHY_CTRL_REG_SOFTRESET_MASK</a>.</p>

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          <td class="memname">u32 XMipi_Rx_Phy_SelfTest </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___rx___phy.html">XMipi_Rx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>Runs a self-test on the driver/device. </p>
<p>This test checks if HS Timeout value present in register matches the one from the generated file.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_mipi___rx___phy.html" title="The Xmipi_rx_phy Controller driver instance data. ">XMipi_Rx_Phy</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if self-test was successful</li>
</ul>
</dd></dl>
<ul>
<li>XST_FAILURE if the read value was not equal to _g.c file</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___rx___phy.html#aacb9702cb804f802478eb4d8c16fca38">XMipi_Rx_Phy::Config</a>, <a class="el" href="struct_x_mipi___rx___phy___config.html#a05e041c93ffdd9e6728c70cc0cd77faf">XMipi_Rx_Phy_Config::HSTimeOut</a>, <a class="el" href="group__mipi__rx__phy.html#ga4149681aae67882912df4493b8e7d66e">XMipi_Rx_Phy_GetInfo()</a>, and <a class="el" href="group__mipi__rx__phy.html#ga72222b2af839769c09e80f143f2da026">XMIPI_RX_PHY_HANDLE_HSTIMEOUT</a>.</p>

<p>Referenced by <a class="el" href="xmipi__rx__phy__example__selftest_8c.html#a6dc882f61ad6323877a35d7bc3c3f6b5">Mipi_Rx_PhySelfTestExample()</a>.</p>

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